{"schemaVersion":"jobsearcher.job.v1","id":"c15f0175fbaafbf5fd39babd","url":"https://jobsearcher.com/jobs/c15f0175fbaafbf5fd39babd","canonicalUrl":"https://jobsearcher.com/jobs/c15f0175fbaafbf5fd39babd","title":"Lead Engineer FPGA DESIGN","description":"We are looking for candidates more on VHDL and FPGA programming side.\nTitle: Lead Engineer – FPGA Design\nLocation: Houston, TX\nDuration – Fulltime\nTechnical Skills\nExpert in implementing digital designs in FPGA using VHDL/Verilog\n· Should be able to develop and own FPGA designs of reasonable complexity\n· Hands-on experience in all FPGA development phases\no RTL coding for synthesis, Testbench development, Functional Simulation, Synthesis, Place and Route, Timing Closure, On board testing\nShould have hands on experience in Zynq FPGA SoCs or similar devices\n· Should have very good understanding of FPGA internals\n· Capability to discuss system level aspects with hardware, software team members\n· Good understanding of simple serial communication protocols like IIC, SPI, UART or similar\n· Experience in timing closure of designs\n· Tool knowledge – Xilinx Vivado or Intel Quartus or ModelSim/QuestaSim or similar EDA tools\nWould be a plus:\n· Exposure to standard interfaces like AXI-4, AXI-S, Ethernet, PCIe etc.\n· · Experience in using Gigabit Transceivers\n· · Experience using DDR memory controllers\n· · Exposure to lint tools, CDC tools\nJob Responsibilities\nUnderstand customer requirements and develop FPGA architecture to meet the requirements\n· Identify independent modules in the FPGA architecture and guide engineers to develop detail design of the module and implement them\n· Ownership of the top-level FPGA design in projects\n· Timing closure of FPGA design\n· Mentor at least four engineers\nCommunication\nGood and strong verbal and written communication to involved stakeholders\nPreferred qualification\nBachelor of Electronics and Communications Engineering\n· Years of Experience : 6 - 9 Years\nJob Type: Full-time\nPay: $110,000.00 - $120,000.00 per year\nSchedule:\n8 hour shift\nAbility to commute/relocate:\nHouston, TX 77001: Reliably commute or planning to relocate before starting work (Required)\nExperience:\nFPGA design - Lead engineer: 6 years (Preferred)\ncandidates more on VHDL and FPGA programming side.: 7 years (Preferred)\nSynthesis, Place and Route, Timing Closure, On board testing: 6 years (Preferred)\nWork Location: In person","company":"Plaxonic Technologies","rawCompany":"plaxonic technologies","city":"Houston","state":"TX","isRemote":false,"isActive":false,"createdAt":"2026-08-04T13:44:07.917Z","occupations":[{"code":"17-2072.00","title":"Electronics Engineers, Except Computer","slug":"electronics-engineers-except-computer"},{"code":"17-2061.00","title":"Computer Hardware Engineers","slug":"computer-hardware-engineers"},{"code":"17-2199.00","title":"Engineers, All Other","slug":"engineers-all-other"}],"industries":[{"code":"334419","title":"Other Electronic Component Manufacturing","slug":"other-electronic-component-manufacturing"},{"code":"334413","title":"Semiconductor and Related Device Manufacturing","slug":"semiconductor-and-related-device-manufacturing"},{"code":"334111","title":"Electronic Computer Manufacturing","slug":"electronic-computer-manufacturing"}],"jobPosting":{"@context":"https://schema.org","@type":"JobPosting","title":"Lead Engineer FPGA DESIGN","description":"We are looking for candidates more on VHDL and FPGA programming side.\nTitle: Lead Engineer – FPGA Design\nLocation: Houston, TX\nDuration – Fulltime\nTechnical Skills\nExpert in implementing digital designs in FPGA using VHDL/Verilog\n· Should be able to develop and own FPGA designs of reasonable complexity\n· Hands-on experience in all FPGA development phases\no RTL coding for synthesis, Testbench development, Functional Simulation, Synthesis, Place and Route, Timing Closure, On board testing\nShould have hands on experience in Zynq FPGA SoCs or similar devices\n· Should have very good understanding of FPGA internals\n· Capability to discuss system level aspects with hardware, software team members\n· Good understanding of simple serial communication protocols like IIC, SPI, UART or similar\n· Experience in timing closure of designs\n· Tool knowledge – Xilinx Vivado or Intel Quartus or ModelSim/QuestaSim or similar EDA tools\nWould be a plus:\n· Exposure to standard interfaces like AXI-4, AXI-S, Ethernet, PCIe etc.\n· · Experience in using Gigabit Transceivers\n· · Experience using DDR memory controllers\n· · Exposure to lint tools, CDC tools\nJob Responsibilities\nUnderstand customer requirements and develop FPGA architecture to meet the requirements\n· Identify independent modules in the FPGA architecture and guide engineers to develop detail design of the module and implement them\n· Ownership of the top-level FPGA design in projects\n· Timing closure of FPGA design\n· Mentor at least four engineers\nCommunication\nGood and strong verbal and written communication to involved stakeholders\nPreferred qualification\nBachelor of Electronics and Communications Engineering\n· Years of Experience : 6 - 9 Years\nJob Type: Full-time\nPay: $110,000.00 - $120,000.00 per year\nSchedule:\n8 hour shift\nAbility to commute/relocate:\nHouston, TX 77001: Reliably commute or planning to relocate before starting work (Required)\nExperience:\nFPGA design - Lead engineer: 6 years (Preferred)\ncandidates more on VHDL and FPGA programming side.: 7 years (Preferred)\nSynthesis, Place and Route, Timing Closure, On board testing: 6 years (Preferred)\nWork Location: In person","datePosted":"2026-08-04T13:44:07.917Z","dateModified":"2026-08-04T13:44:07.917Z","hiringOrganization":{"@type":"Organization","name":"Plaxonic Technologies","sameAs":"https://jobsearcher.com"},"jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Houston","addressRegion":"TX","addressCountry":"US"}},"identifier":{"@type":"PropertyValue","name":"JobSearcher","value":"c15f0175fbaafbf5fd39babd"},"url":"https://jobsearcher.com/jobs/c15f0175fbaafbf5fd39babd"}}