{"schemaVersion":"jobsearcher.job.v1","id":"c0787e138ef4e078a1771f0d","url":"https://jobsearcher.com/jobs/c0787e138ef4e078a1771f0d","canonicalUrl":"https://jobsearcher.com/jobs/c0787e138ef4e078a1771f0d","title":"Memory Interface PHY IP, Design Engineering Architect","description":"At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.A Design Engineering Architect provides the technical leadership needed to translate evolving standards and customer requirements into scalable, high‑quality IP architectures. This role reduces execution risk, accelerates customer engagements, and strengthens long‑term product competitiveness.Design Engineering Architect – Roles & ResponsibilitiesContribute to PHY architecture development with deep understanding of memory interface PHY IPs (e.g., DDR, LPDDR), including electrical, timing, power, and protocol considerationsDrive architecture decisions aligned with JEDEC standards, protocols, and compliance requirementsGood understanding of PHY/IO circuit architecture including TX/RX, clocking, termination, power delivery, and signal integrity trade‑offsAct as a customer‑facing technical architect during pre‑sales, evaluations, and post‑delivery support, clearly articulating architecture choices and trade‑offsCollaborate closely with Sales, Marketing, and Program teams to support customer engagements, RFIs, and technical proposalsProvide expert‑level IP support to customers, including architecture clarification, feature customizationWork cross‑functionally with design, verification, layout, and silicon validation teams to ensure architectural intent is correctly implementedReview and guide architecture specifications, design reviews, and technical documentationInfluence product and technology roadmap planning by identifying future standards, protocol evolution, and customer‑driven requirementsDemonstrate strong communication, accountability, and technical ownership across internal and external interactionsRequired QualificationsM.S. degree in Electrical Engineering, Computer Engineering, or related fieldMinimum 15 years of industry experience in memory interface PHY, high‑speed IO, or related domainsStrong background in memory interface PHYs, JEDEC standards, and protocolsProven ability to own customer‑facing technical engagements and drive issues to closureExcellent written and verbal communication skillsThe annual salary range for California is $136,500 to $253,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.We’re doing work that matters. Help us solve what others can’t.","company":"Cadence","rawCompany":"cadence","city":"San Jose","state":"CA","isRemote":false,"isActive":false,"createdAt":"2026-07-11T10:54:53.763Z","occupations":[{"code":"17-2072.00","title":"Electronics Engineers, Except Computer","slug":"electronics-engineers-except-computer"},{"code":"17-2061.00","title":"Computer Hardware Engineers","slug":"computer-hardware-engineers"},{"code":"15-1299.08","title":"Computer Systems Engineers/Architects","slug":"computer-systems-engineers-architects"}],"industries":[{"code":"334413","title":"Semiconductor and Related Device Manufacturing","slug":"semiconductor-and-related-device-manufacturing"},{"code":"334111","title":"Electronic Computer Manufacturing","slug":"electronic-computer-manufacturing"},{"code":"541512","title":"Computer Systems Design Services","slug":"computer-systems-design-services"}],"jobPosting":{"@context":"https://schema.org","@type":"JobPosting","title":"Memory Interface PHY IP, Design Engineering Architect","description":"At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.A Design Engineering Architect provides the technical leadership needed to translate evolving standards and customer requirements into scalable, high‑quality IP architectures. This role reduces execution risk, accelerates customer engagements, and strengthens long‑term product competitiveness.Design Engineering Architect – Roles & ResponsibilitiesContribute to PHY architecture development with deep understanding of memory interface PHY IPs (e.g., DDR, LPDDR), including electrical, timing, power, and protocol considerationsDrive architecture decisions aligned with JEDEC standards, protocols, and compliance requirementsGood understanding of PHY/IO circuit architecture including TX/RX, clocking, termination, power delivery, and signal integrity trade‑offsAct as a customer‑facing technical architect during pre‑sales, evaluations, and post‑delivery support, clearly articulating architecture choices and trade‑offsCollaborate closely with Sales, Marketing, and Program teams to support customer engagements, RFIs, and technical proposalsProvide expert‑level IP support to customers, including architecture clarification, feature customizationWork cross‑functionally with design, verification, layout, and silicon validation teams to ensure architectural intent is correctly implementedReview and guide architecture specifications, design reviews, and technical documentationInfluence product and technology roadmap planning by identifying future standards, protocol evolution, and customer‑driven requirementsDemonstrate strong communication, accountability, and technical ownership across internal and external interactionsRequired QualificationsM.S. degree in Electrical Engineering, Computer Engineering, or related fieldMinimum 15 years of industry experience in memory interface PHY, high‑speed IO, or related domainsStrong background in memory interface PHYs, JEDEC standards, and protocolsProven ability to own customer‑facing technical engagements and drive issues to closureExcellent written and verbal communication skillsThe annual salary range for California is $136,500 to $253,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.We’re doing work that matters. Help us solve what others can’t.","datePosted":"2026-07-11T10:54:53.763Z","dateModified":"2026-07-11T10:54:53.763Z","hiringOrganization":{"@type":"Organization","name":"Cadence","sameAs":"https://jobsearcher.com"},"jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"San Jose","addressRegion":"CA","addressCountry":"US"}},"identifier":{"@type":"PropertyValue","name":"JobSearcher","value":"c0787e138ef4e078a1771f0d"},"url":"https://jobsearcher.com/jobs/c0787e138ef4e078a1771f0d"}}