{"schemaVersion":"jobsearcher.job.v1","id":"c069cd435e83defb944f3049","url":"https://jobsearcher.com/jobs/c069cd435e83defb944f3049","canonicalUrl":"https://jobsearcher.com/jobs/c069cd435e83defb944f3049","title":"Lead Diagnostics Software Engineer, ATE Integration","description":"Overview\nAs a diagnostics leader in a shift-left validation program, you will translate post-silicon testing into production-grade ATE and wafer-sort workflows. You’ll bridge software and hardware test domains, architecting tooling to stream complex GFX/compute tests into deterministic, high-coverage patterns. This high-impact role emphasizes cross-domain collaboration, scalable test architectures, and manufacturing-focused quality at scale. You will shape the validation strategy for data-center GPU IPs and HBM/multi-die architectures in a fast-paced, innovative environment.\n\nResponsibilitiesDefine the technical roadmap and deployment strategy to migrate SLT and GFX diagnostics onto wafer-sort and ATE hardwareArchitect software pipelines to convert diagnostic sequences, configurations, and workloads into cycle-accurate vector formats (e.g., STIL, WGL) for ATE testersServe as liaison between GFX/Compute Diagnostics, Product/Test Engineering, and DFT teamsAnalyze platform dependencies to build deterministic models that emulate host behaviors on ATE hardwareOptimize tester execution times while maximizing structural/functional coverage for data center GPU IPs (HBM, matrix engines)\nKey requirements8+ years in silicon engineering or equivalent (post-silicon validation, diagnostics, or test generation)Strong programming in C/C++ and Python; knowledge of bare-metal/driver-level programming and firmwareHands-on experience with production-grade ATE platforms (e.g., V93000, UltraFLEX) and wafer sort/final testExpert understanding of pattern generation, vector timing, clock domains, and diagnostic patterns (BIST/MBIST, scan)Familiarity with data-center manufacturing challenges (HBM, multi-die chiplets, UCIe)Understanding of GFX/compute architectures and diagnostic/test case design for high coverageKnowledge of AI/ML concepts and some experience applying LLM/ML in applicationsDevOps experience (GitHub, CI/CD)Excellent problem-solving and detail orientationcollaborativedetail-orientedproblem-solverC/C++ programmingPython programmingbare-metal/driver-level programming","company":"AMD","rawCompany":"amd","city":"Chicago","state":"IL","isRemote":false,"isActive":true,"createdAt":"2026-09-15T04:28:59.700Z","occupations":[{"code":"17-2061.00","title":"Computer Hardware Engineers","slug":"computer-hardware-engineers"},{"code":"15-1299.08","title":"Computer Systems Engineers/Architects","slug":"computer-systems-engineers-architects"},{"code":"17-2112.02","title":"Validation Engineers","slug":"validation-engineers"}],"industries":[{"code":"541512","title":"Computer Systems Design Services","slug":"computer-systems-design-services"},{"code":"334413","title":"Semiconductor and Related Device Manufacturing","slug":"semiconductor-and-related-device-manufacturing"},{"code":"334111","title":"Electronic Computer Manufacturing","slug":"electronic-computer-manufacturing"}],"jobPosting":{"@context":"https://schema.org","@type":"JobPosting","title":"Lead Diagnostics Software Engineer, ATE Integration","description":"Overview\nAs a diagnostics leader in a shift-left validation program, you will translate post-silicon testing into production-grade ATE and wafer-sort workflows. You’ll bridge software and hardware test domains, architecting tooling to stream complex GFX/compute tests into deterministic, high-coverage patterns. This high-impact role emphasizes cross-domain collaboration, scalable test architectures, and manufacturing-focused quality at scale. You will shape the validation strategy for data-center GPU IPs and HBM/multi-die architectures in a fast-paced, innovative environment.\n\nResponsibilitiesDefine the technical roadmap and deployment strategy to migrate SLT and GFX diagnostics onto wafer-sort and ATE hardwareArchitect software pipelines to convert diagnostic sequences, configurations, and workloads into cycle-accurate vector formats (e.g., STIL, WGL) for ATE testersServe as liaison between GFX/Compute Diagnostics, Product/Test Engineering, and DFT teamsAnalyze platform dependencies to build deterministic models that emulate host behaviors on ATE hardwareOptimize tester execution times while maximizing structural/functional coverage for data center GPU IPs (HBM, matrix engines)\nKey requirements8+ years in silicon engineering or equivalent (post-silicon validation, diagnostics, or test generation)Strong programming in C/C++ and Python; knowledge of bare-metal/driver-level programming and firmwareHands-on experience with production-grade ATE platforms (e.g., V93000, UltraFLEX) and wafer sort/final testExpert understanding of pattern generation, vector timing, clock domains, and diagnostic patterns (BIST/MBIST, scan)Familiarity with data-center manufacturing challenges (HBM, multi-die chiplets, UCIe)Understanding of GFX/compute architectures and diagnostic/test case design for high coverageKnowledge of AI/ML concepts and some experience applying LLM/ML in applicationsDevOps experience (GitHub, CI/CD)Excellent problem-solving and detail orientationcollaborativedetail-orientedproblem-solverC/C++ programmingPython programmingbare-metal/driver-level programming","datePosted":"2026-09-15T04:28:59.700Z","dateModified":"2026-09-15T04:28:59.700Z","hiringOrganization":{"@type":"Organization","name":"AMD","sameAs":"https://jobsearcher.com"},"jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Chicago","addressRegion":"IL","addressCountry":"US"}},"identifier":{"@type":"PropertyValue","name":"JobSearcher","value":"c069cd435e83defb944f3049"},"url":"https://jobsearcher.com/jobs/c069cd435e83defb944f3049"}}