{"schemaVersion":"jobsearcher.job.v1","id":"bc11d6a915906501be81752c","url":"https://jobsearcher.com/jobs/bc11d6a915906501be81752c","canonicalUrl":"https://jobsearcher.com/jobs/bc11d6a915906501be81752c","title":"Memory Controller Designer/RTL Engineer","description":"Notes from the HM Call:\nAustin, TX will be preferred. San Jose & San Diego secondary location.\n\nDuration: 6 months\n\nA.Hebbar: https://www.linkedin.com/in/ akarsh /\n\nLPDDR & Memory Controller is a must.\n\nKnowledge of memory controller u-architecture.\n\nFamiliarity with different memory technologies like LPDDR4 /5, HBM.\n\nKnowledge of JEDEC memory standards preferred.\n\nKnowledge of AES, ECC, RAS features preferred.\n\nRTL design\n\nASIC design flow would be good to have\n\n10+ yrs of work experience.\n\n1 st round-phone screen of 45mins – 1hr.\n\n2 nd round- Panel interview of 2 - 2: 30hrs .- Austin or San Jose- Onsite, San Diego- Virtual\n\nLocation: Austin [Preferred], 2nd -San Jose or 3rd -San Diego\n\nHybrid 3x per week\nJob Description Summary\n\nSamsung is a world leader in Memory, LCD and System LSI technologies that has the vision and commitment to invest in the future of technology – demonstrated by the $17B investment in the new 3nm Fab in Texas and the commitment to invest in dramatically expanding design activities across GPU, System IP and SoC Architecture. We are currently looking for exceptional software and hardware engineers to join our System IP team in our Austin, TX R & D Center (SARC) and our Advanced Computing Lab (ACL) in San Jose, CA. Our System IP team develops proprietary coherent interconnect and memory controller deployed in many high volume products.\n\nJob Description\n\nAs a senior designer on custom memory controller micro-architect, you will be responsible for working on the micro-architecture development of custom memory controller for LPDDR5, LP. In this role you will be interacting with the system architects, verification, performance/power and design implementation teams. You will be owning and driving the critical memory controller related RTL design, performance and power optimization and also work on logic debug and timing closure of the design. Solid engineer foundation and RTL design experience are desired for success.\n\nKey responsibilities include:\nDrive the timely development and debug of new features on timely development of custom memory controller.\n\nWorking on SOC IP delivery with all sanity checks.\n\nWork on timing debug and closure.\n\nWorking on LINT, CDC flows and analysis.\n\nWork on power artist flow and power analysis.\n\nWorking on ECO flows.\n\nWork with the verification team to verify the functionality and correctness of the design.\n\nCollaborate with implementation to achieve your timing and area.\n\nProduce quality RTL on schedule meeting PPA goals\n\nEngage with performance and power team on achieving performance and power goals.\n\nPartner with the physical design and CAD team to resolve implementation level details.\n\nPreferred candidate will possess the following:\nPhD, Master's Degree or Bachelor's Degree , Computer Engineer with over 10+ years of experience.\n\nStrong background owning and driving the RTL design of various sub-blocks of custom memory controller designs\n\nDemonstrated experience of successful Architectural through RTL design experience on high performance digital designs\n\nVerilog expertise is required as is a deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis & ECO.\n\nKnowledge of memory controller u-architecture.\n\nFamiliarity with different memory technologies like LPDDR4/5, HBM.\n\nKnowledge of JEDEC memory standards preferred.\n\nKnowledge of AES, ECC, RAS features preferred.\n\nStrong communication and interpersonal skills are required along with the ability to work in a dynamic, global team.\n\nExperience with a scripting language like Perl or Python.\n\nEnergetic, curiosity, and passion in logic design.\n\nGood written and verbal communication skills.","company":"Bayone","rawCompany":"bayone","city":"Austin","state":"TX","isRemote":false,"isActive":false,"createdAt":"2026-08-10T13:39:03.734Z","occupations":[{"code":"17-2072.00","title":"Electronics Engineers, Except Computer","slug":"electronics-engineers-except-computer"},{"code":"17-2061.00","title":"Computer Hardware Engineers","slug":"computer-hardware-engineers"},{"code":"17-2199.06","title":"Microsystems Engineers","slug":"microsystems-engineers"}],"industries":[{"code":"334413","title":"Semiconductor and Related Device Manufacturing","slug":"semiconductor-and-related-device-manufacturing"},{"code":"334111","title":"Electronic Computer Manufacturing","slug":"electronic-computer-manufacturing"},{"code":"541512","title":"Computer Systems Design Services","slug":"computer-systems-design-services"}],"jobPosting":{"@context":"https://schema.org","@type":"JobPosting","title":"Memory Controller Designer/RTL Engineer","description":"Notes from the HM Call:\nAustin, TX will be preferred. San Jose & San Diego secondary location.\n\nDuration: 6 months\n\nA.Hebbar: https://www.linkedin.com/in/ akarsh /\n\nLPDDR & Memory Controller is a must.\n\nKnowledge of memory controller u-architecture.\n\nFamiliarity with different memory technologies like LPDDR4 /5, HBM.\n\nKnowledge of JEDEC memory standards preferred.\n\nKnowledge of AES, ECC, RAS features preferred.\n\nRTL design\n\nASIC design flow would be good to have\n\n10+ yrs of work experience.\n\n1 st round-phone screen of 45mins – 1hr.\n\n2 nd round- Panel interview of 2 - 2: 30hrs .- Austin or San Jose- Onsite, San Diego- Virtual\n\nLocation: Austin [Preferred], 2nd -San Jose or 3rd -San Diego\n\nHybrid 3x per week\nJob Description Summary\n\nSamsung is a world leader in Memory, LCD and System LSI technologies that has the vision and commitment to invest in the future of technology – demonstrated by the $17B investment in the new 3nm Fab in Texas and the commitment to invest in dramatically expanding design activities across GPU, System IP and SoC Architecture. We are currently looking for exceptional software and hardware engineers to join our System IP team in our Austin, TX R & D Center (SARC) and our Advanced Computing Lab (ACL) in San Jose, CA. Our System IP team develops proprietary coherent interconnect and memory controller deployed in many high volume products.\n\nJob Description\n\nAs a senior designer on custom memory controller micro-architect, you will be responsible for working on the micro-architecture development of custom memory controller for LPDDR5, LP. In this role you will be interacting with the system architects, verification, performance/power and design implementation teams. You will be owning and driving the critical memory controller related RTL design, performance and power optimization and also work on logic debug and timing closure of the design. Solid engineer foundation and RTL design experience are desired for success.\n\nKey responsibilities include:\nDrive the timely development and debug of new features on timely development of custom memory controller.\n\nWorking on SOC IP delivery with all sanity checks.\n\nWork on timing debug and closure.\n\nWorking on LINT, CDC flows and analysis.\n\nWork on power artist flow and power analysis.\n\nWorking on ECO flows.\n\nWork with the verification team to verify the functionality and correctness of the design.\n\nCollaborate with implementation to achieve your timing and area.\n\nProduce quality RTL on schedule meeting PPA goals\n\nEngage with performance and power team on achieving performance and power goals.\n\nPartner with the physical design and CAD team to resolve implementation level details.\n\nPreferred candidate will possess the following:\nPhD, Master's Degree or Bachelor's Degree , Computer Engineer with over 10+ years of experience.\n\nStrong background owning and driving the RTL design of various sub-blocks of custom memory controller designs\n\nDemonstrated experience of successful Architectural through RTL design experience on high performance digital designs\n\nVerilog expertise is required as is a deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis & ECO.\n\nKnowledge of memory controller u-architecture.\n\nFamiliarity with different memory technologies like LPDDR4/5, HBM.\n\nKnowledge of JEDEC memory standards preferred.\n\nKnowledge of AES, ECC, RAS features preferred.\n\nStrong communication and interpersonal skills are required along with the ability to work in a dynamic, global team.\n\nExperience with a scripting language like Perl or Python.\n\nEnergetic, curiosity, and passion in logic design.\n\nGood written and verbal communication skills.","datePosted":"2026-08-10T13:39:03.734Z","dateModified":"2026-08-10T13:39:03.734Z","hiringOrganization":{"@type":"Organization","name":"Bayone","sameAs":"https://jobsearcher.com"},"jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Austin","addressRegion":"TX","addressCountry":"US"}},"identifier":{"@type":"PropertyValue","name":"JobSearcher","value":"bc11d6a915906501be81752c"},"url":"https://jobsearcher.com/jobs/bc11d6a915906501be81752c"}}