Layout Design Engineer

CMOS Layout Design Engineer – High-Speed Logic & PhotonicsA well-funded deep-tech semiconductor company is developing next-generation computing and connectivity technologies that combine advanced CMOS design with integrated photonics.The organization is building highly complex silicon platforms designed to overcome performance and efficiency limitations in modern computing systems. Their multidisciplinary engineering teams work across IC design, photonics, packaging, and systems engineering to develop cutting-edge hardware for emerging compute-intensive applications.We are seeking a CMOS Layout Design Engineer to join a growing IC design team focused on custom layout development for high-speed analog, mixed-signal, and photonic integrated circuits.Role OverviewThis role is responsible for full-custom CMOS layout development from block-level implementation through top-level integration and tape-out.The engineer will work closely with circuit designers to optimize layouts for performance, noise, reliability, and manufacturability while supporting advanced CMOS technologies and monolithically integrated photonic components.This position requires strong expertise in analog and mixed-signal layout techniques, physical verification, and tape-out execution within advanced semiconductor processes.Key ResponsibilitiesDevelop full-custom layout for analog, mixed-signal, and high-speed circuit blocksPerform block-level and top-level physical integration activitiesApply advanced layout methodologies including device matching, common-centroid placement, symmetry techniques, shielding, and critical-net routingOptimize layouts to minimize parasitic effects and maximize circuit performanceSupport integration of photonic structures within CMOS process technologiesParticipate in floorplanning, routing strategy, and physical design reviewsImplement ESD structures, I/O ring integration, and padframe layoutsExecute physical verification flows including DRC, LVS, parasitic extraction, and tape-out signoffCollaborate closely with design engineers to resolve layout-driven performance issuesSupport engineering change orders and late-stage design modificationsRequired QualificationsBachelor's degree in Electrical Engineering or a related discipline5+ years of experience in custom CMOS layout designStrong experience with analog and mixed-signal layout techniquesExpertise in device matching, symmetry, common-centroid structures, and parasitic-aware layout practicesExperience with advanced CMOS process technologiesProficiency with Cadence Virtuoso Layout XL/GXLExperience with physical verification tools such as Calibre or equivalentFamiliarity with parasitic extraction and tape-out methodologiesExperience implementing ESD structures and pad frame integrationPreferred QualificationsExperience with high-speed logic or mixed-signal circuitsExposure to photonic integrated circuits or silicon photonics technologiesKnowledge of reliability considerations including electromigration, IR drop, and latch-up preventionExperience with SKILL, Python, or layout automation methodologiesPrior experience supporting advanced-node tape-outsCompensation & BenefitsCompetitive base salary ($190K-$210K) and bonus opportunityComprehensive medical, dental, and vision coverageRetirement savings programGenerous paid time offOpportunity to work on industry-leading semiconductor and photonics technologiesCollaborative environment with strong technical ownership and career growth opportunitiesCMOS Layout Engineer, Custom Layout Engineer, Analog Layout Engineer, Mixed-Signal Layout Engineer, Physical Layout Engineer, IC Layout Engineer, Custom IC Layout, Cadence Virtuoso, Calibre, DRC, LVS, PEX, Tape-Out, Analog IC Design, Mixed-Signal IC Design, Semiconductor Design, Silicon Photonics, Photonic Integrated Circuits, High-Speed Logic