{"schemaVersion":"jobsearcher.job.v1","id":"b83c9bf4bf431ffddc02bf79","url":"https://jobsearcher.com/jobs/b83c9bf4bf431ffddc02bf79","canonicalUrl":"https://jobsearcher.com/jobs/b83c9bf4bf431ffddc02bf79","title":"DFT Engineer","description":"DFT EngineerSanta Clara, CA Onsite roleFulltime/Permanent role.Role PurposeWe are hiring a DFT Engineer with hands-on experience in Scan, ATPG, MBIST, or Boundary ScanKey Responsibilities:Work on Scan insertion, ATPG, GLS (timing/non-timing)Implement MBIST and/or Boundary Scan (BSCAN, JTAG)Support DFT architecture and chip-level integrationDebug DFT issues and improve test coverageRequirements:Experience in at least 2 DFT areas (Scan/ATPG/MBIST/BSCAN/GLS)Strong understanding of DFT concepts and flowExposure to end-to-end DFT is a plus","company":"Programmers.io","rawCompany":"programmersio","city":"San Jose","state":"CA","isRemote":false,"isActive":false,"createdAt":"2026-06-17T01:00:28.495Z","occupations":[{"code":"15-1299.08","title":"Computer Systems Engineers/Architects","slug":"computer-systems-engineers-architects"},{"code":"17-2199.00","title":"Engineers, All Other","slug":"engineers-all-other"},{"code":"17-2072.00","title":"Electronics Engineers, Except Computer","slug":"electronics-engineers-except-computer"}],"industries":[{"code":"541512","title":"Computer Systems Design Services","slug":"computer-systems-design-services"},{"code":"334413","title":"Semiconductor and Related Device Manufacturing","slug":"semiconductor-and-related-device-manufacturing"},{"code":"334419","title":"Other Electronic Component Manufacturing","slug":"other-electronic-component-manufacturing"}],"jobPosting":{"@context":"https://schema.org","@type":"JobPosting","title":"DFT Engineer","description":"DFT EngineerSanta Clara, CA Onsite roleFulltime/Permanent role.Role PurposeWe are hiring a DFT Engineer with hands-on experience in Scan, ATPG, MBIST, or Boundary ScanKey Responsibilities:Work on Scan insertion, ATPG, GLS (timing/non-timing)Implement MBIST and/or Boundary Scan (BSCAN, JTAG)Support DFT architecture and chip-level integrationDebug DFT issues and improve test coverageRequirements:Experience in at least 2 DFT areas (Scan/ATPG/MBIST/BSCAN/GLS)Strong understanding of DFT concepts and flowExposure to end-to-end DFT is a plus","datePosted":"2026-06-17T01:00:28.495Z","dateModified":"2026-06-17T01:00:28.495Z","hiringOrganization":{"@type":"Organization","name":"Programmers.io","sameAs":"https://jobsearcher.com"},"jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"San Jose","addressRegion":"CA","addressCountry":"US"}},"identifier":{"@type":"PropertyValue","name":"JobSearcher","value":"b83c9bf4bf431ffddc02bf79"},"url":"https://jobsearcher.com/jobs/b83c9bf4bf431ffddc02bf79"}}