{"schemaVersion":"jobsearcher.job.v1","id":"b67a7e1ab38b169d5eafe4cf","url":"https://jobsearcher.com/jobs/b67a7e1ab38b169d5eafe4cf","canonicalUrl":"https://jobsearcher.com/jobs/b67a7e1ab38b169d5eafe4cf","title":"Lead Test Development Engineer","description":"Overview\nAs Lead Test Development Engineer, you will shape manufacturing test solutions for Achronix’s FPGA portfolio. You’ll lead the definition and implementation of DFT to enable reliable high-performance silicon from early bring-up to high-volume production. You’ll partner with design, product, and manufacturing teams to improve test coverage and optimize test time, delivering robust test programs and automation. This role offers impact across RTL to production, with a focus on scalable, verifiable test technology and cross-functional collaboration.\n\nResponsibilitiesDefine and implement DFT architecture (scan, boundary scan IEEE 1149.1/1687, MBIST) and related featuresCollaborate with design and physical design teams to verify DFT at RTL and gate levelsDesign test mode controls and access mechanisms to support effective testing and verificationGenerate and validate ATPG patterns for stuck-at, transition delay, and path delay faultsTarget test cases for FPGA blocks and IP, including reconfigurable core fabric, DSPs, and embedded memoriesIntegrate testing solutions for external memory interfaces (DDR5, GDDR6) and high-speed I/O interfaces (SerDes, PCIe, Ethernet)Perform fault coverage analysis and implement improvementsConduct gate-level simulations with test patterns for timing closurePerform silicon pattern bring-up, validation, and debugging on lab bench and ATE platformsImplement and debug scan, BIST, and functional tests on production testersAnalyze yield issues and correlate silicon data with design and DFT logicDevelop and maintain scripts to automate pattern generation, simulation, data analysis, and ATE format conversionMaintain and improve internal DFT/test infrastructure workflowsCollaborate with design, verification, product engineering, and manufacturing teams to ensure testability and high-quality silicon\nKey requirements10+ years of experience in DFT, testing, or silicon validationSolid understanding of scan insertion, ATPG, MBIST, and fault modelsExperience with Synopsys TestMax, Siemens Tessent, and similar DFT EDA toolsProficiency with JTAG, boundary scan, and IEEE 1149.1/1149.6 standardsHands-on experience with ATPG, MBIST, functional pattern generation, simulation, and verificationFamiliar with script-based test case generators and industry-standard test pattern formats (WGL, STIL)Proficiency in scripting languages (Python, Perl, or Tcl)Strong debugging and problem-solving skills for silicon and test issuesCross-functional collaborationStrong debugging and problem-solvingProactive communicationDFT architecture and implementation (scan, boundary scan, MBIST)ATPG and fault modelsDFT EDA tools (Synopsys TestMax, Siemens Tessent)","company":"Achronix Semiconductor","rawCompany":"achronix semiconductor","city":"San Jose","state":"CA","isRemote":false,"isActive":false,"createdAt":"2026-09-15T03:50:45.824Z","occupations":[{"code":"17-2072.00","title":"Electronics Engineers, Except Computer","slug":"electronics-engineers-except-computer"},{"code":"17-2112.02","title":"Validation Engineers","slug":"validation-engineers"},{"code":"15-1253.00","title":"Software Quality Assurance Analysts and Testers","slug":"software-quality-assurance-analysts-and-testers"}],"industries":[{"code":"334413","title":"Semiconductor and Related Device Manufacturing","slug":"semiconductor-and-related-device-manufacturing"},{"code":"541512","title":"Computer Systems Design Services","slug":"computer-systems-design-services"},{"code":"334111","title":"Electronic Computer Manufacturing","slug":"electronic-computer-manufacturing"}],"jobPosting":{"@context":"https://schema.org","@type":"JobPosting","title":"Lead Test Development Engineer","description":"Overview\nAs Lead Test Development Engineer, you will shape manufacturing test solutions for Achronix’s FPGA portfolio. You’ll lead the definition and implementation of DFT to enable reliable high-performance silicon from early bring-up to high-volume production. You’ll partner with design, product, and manufacturing teams to improve test coverage and optimize test time, delivering robust test programs and automation. This role offers impact across RTL to production, with a focus on scalable, verifiable test technology and cross-functional collaboration.\n\nResponsibilitiesDefine and implement DFT architecture (scan, boundary scan IEEE 1149.1/1687, MBIST) and related featuresCollaborate with design and physical design teams to verify DFT at RTL and gate levelsDesign test mode controls and access mechanisms to support effective testing and verificationGenerate and validate ATPG patterns for stuck-at, transition delay, and path delay faultsTarget test cases for FPGA blocks and IP, including reconfigurable core fabric, DSPs, and embedded memoriesIntegrate testing solutions for external memory interfaces (DDR5, GDDR6) and high-speed I/O interfaces (SerDes, PCIe, Ethernet)Perform fault coverage analysis and implement improvementsConduct gate-level simulations with test patterns for timing closurePerform silicon pattern bring-up, validation, and debugging on lab bench and ATE platformsImplement and debug scan, BIST, and functional tests on production testersAnalyze yield issues and correlate silicon data with design and DFT logicDevelop and maintain scripts to automate pattern generation, simulation, data analysis, and ATE format conversionMaintain and improve internal DFT/test infrastructure workflowsCollaborate with design, verification, product engineering, and manufacturing teams to ensure testability and high-quality silicon\nKey requirements10+ years of experience in DFT, testing, or silicon validationSolid understanding of scan insertion, ATPG, MBIST, and fault modelsExperience with Synopsys TestMax, Siemens Tessent, and similar DFT EDA toolsProficiency with JTAG, boundary scan, and IEEE 1149.1/1149.6 standardsHands-on experience with ATPG, MBIST, functional pattern generation, simulation, and verificationFamiliar with script-based test case generators and industry-standard test pattern formats (WGL, STIL)Proficiency in scripting languages (Python, Perl, or Tcl)Strong debugging and problem-solving skills for silicon and test issuesCross-functional collaborationStrong debugging and problem-solvingProactive communicationDFT architecture and implementation (scan, boundary scan, MBIST)ATPG and fault modelsDFT EDA tools (Synopsys TestMax, Siemens Tessent)","datePosted":"2026-09-15T03:50:45.824Z","dateModified":"2026-09-15T03:50:45.824Z","hiringOrganization":{"@type":"Organization","name":"Achronix Semiconductor","sameAs":"https://jobsearcher.com"},"jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"San Jose","addressRegion":"CA","addressCountry":"US"}},"identifier":{"@type":"PropertyValue","name":"JobSearcher","value":"b67a7e1ab38b169d5eafe4cf"},"url":"https://jobsearcher.com/jobs/b67a7e1ab38b169d5eafe4cf"}}