{"schemaVersion":"jobsearcher.job.v1","id":"b5f0c48923400a91ea8597b2","url":"https://jobsearcher.com/jobs/b5f0c48923400a91ea8597b2","canonicalUrl":"https://jobsearcher.com/jobs/b5f0c48923400a91ea8597b2","title":"EDA CAD Engineer","description":"EDA Cad Engineer Location: PHOENIX AZ (Remote) – Need local from AZ with address proof Domain: Semiconductor Design and Development Video Interview Ideally looking for applicants with a solid background in Semiconductor Design and Development, Electronic Design Automation (EDA). EDA CAD Engineer job responsibilities include: An experienced CAD/Automation Engineer with experience in digital ASIC design and verification and will develop IP packaging and qualification flow for internal use and external delivery. Must-have skills for this role: A minimum of five years of experience with ASIC Design (RTL2GDS), CAD Automation and RTL Design Verification Electrical Engineering Semiconductor Design and Development. The Work: Scripting and automation of design database qualification and packaging Integration of silicon foundry libraries & technology data, including 4nm, for SOC implementation, verification & packaging Creation of IP packaging flow of design and verification components Checks, validation & qualification of IP package consistency Propagation of IP implementation flow requirements with internal IP teams Support and maintenance of qualification tools and scripts (lint, CDC, sim) Running of stand-alone IP testbench for qualification Initial debug of failures and issues and work w/ IP teams for resolution Maintaining package and release timelines for various projects Working with cross functional teams (DV/Arch/Design/FW) to ensure quality and completeness of release collateral Experience with development of fully automated flows Strong Python & Tcl scripting skills Strong Unix, Shell, Makefile skills Knowledge of ASIC design flow & automation, testbench integration Familiarity with EDA vendors (e.g. Synopsys/Cadence) reference methodology Knowledge of low level HW/SW interaction and debug Experience with RTL & Gate Level Simulations Experience with power analysis methodology","company":"Kasmo Global","rawCompany":"kasmo global","city":"Remote","state":"OR","isRemote":false,"isActive":false,"createdAt":"2026-08-14T22:58:02.448Z","occupations":[{"code":"17-2072.00","title":"Electronics Engineers, Except Computer","slug":"electronics-engineers-except-computer"},{"code":"17-2112.02","title":"Validation Engineers","slug":"validation-engineers"},{"code":"17-2061.00","title":"Computer Hardware Engineers","slug":"computer-hardware-engineers"}],"industries":[{"code":"334413","title":"Semiconductor and Related Device Manufacturing","slug":"semiconductor-and-related-device-manufacturing"},{"code":"334419","title":"Other Electronic Component Manufacturing","slug":"other-electronic-component-manufacturing"},{"code":"334418","title":"Printed Circuit Assembly (Electronic Assembly) Manufacturing","slug":"printed-circuit-assembly-electronic-assembly-manufacturing"}],"jobPosting":{"@context":"https://schema.org","@type":"JobPosting","title":"EDA CAD Engineer","description":"EDA Cad Engineer Location: PHOENIX AZ (Remote) – Need local from AZ with address proof Domain: Semiconductor Design and Development Video Interview Ideally looking for applicants with a solid background in Semiconductor Design and Development, Electronic Design Automation (EDA). EDA CAD Engineer job responsibilities include: An experienced CAD/Automation Engineer with experience in digital ASIC design and verification and will develop IP packaging and qualification flow for internal use and external delivery. Must-have skills for this role: A minimum of five years of experience with ASIC Design (RTL2GDS), CAD Automation and RTL Design Verification Electrical Engineering Semiconductor Design and Development. The Work: Scripting and automation of design database qualification and packaging Integration of silicon foundry libraries & technology data, including 4nm, for SOC implementation, verification & packaging Creation of IP packaging flow of design and verification components Checks, validation & qualification of IP package consistency Propagation of IP implementation flow requirements with internal IP teams Support and maintenance of qualification tools and scripts (lint, CDC, sim) Running of stand-alone IP testbench for qualification Initial debug of failures and issues and work w/ IP teams for resolution Maintaining package and release timelines for various projects Working with cross functional teams (DV/Arch/Design/FW) to ensure quality and completeness of release collateral Experience with development of fully automated flows Strong Python & Tcl scripting skills Strong Unix, Shell, Makefile skills Knowledge of ASIC design flow & automation, testbench integration Familiarity with EDA vendors (e.g. Synopsys/Cadence) reference methodology Knowledge of low level HW/SW interaction and debug Experience with RTL & Gate Level Simulations Experience with power analysis methodology","datePosted":"2026-08-14T22:58:02.448Z","dateModified":"2026-08-14T22:58:02.448Z","hiringOrganization":{"@type":"Organization","name":"Kasmo Global","sameAs":"https://jobsearcher.com"},"jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Remote","addressRegion":"OR","addressCountry":"US"}},"identifier":{"@type":"PropertyValue","name":"JobSearcher","value":"b5f0c48923400a91ea8597b2"},"url":"https://jobsearcher.com/jobs/b5f0c48923400a91ea8597b2"}}