{"schemaVersion":"jobsearcher.job.v1","id":"b521d315074ca905cace7cf9","url":"https://jobsearcher.com/jobs/b521d315074ca905cace7cf9","canonicalUrl":"https://jobsearcher.com/jobs/b521d315074ca905cace7cf9","title":"Digital Implementation Engineer","description":"About the RoleThe chip program runs the standard sequence — architecture, microarchitecture, RTL, verification, implementation, sign-off — and implementation is where the design becomes physically realizable or it does not.\r\nThis is not a standard‑cell autopilot job.\r\nYou will own the digital implementation flow end to end: synthesis through floorplanning, placement, clock tree synthesis, routing, power grid design and IR analysis, and timing closure to tape‑out‑ready GDSII. You will work directly with RTL design, design verification, and the sign‑off engineer in a flat, matrixed organization. When the tool flow does not have the script you need, you will write it. When timing will not close the way the textbook says it should, you will figure out which assumption failed and produce the flow that does close.\r\nIn twelve months, the implementation flow you stand up should be the one every block routes through and the one every sign‑off engineer trusts the inputs from. The scripts, recipes, and methodology you write become the baseline every future implementation engineer at Snowcap inherits.\r\nWhat You'll OwnOwn the physical implementation of digital logic from synthesized netlist through tape‑out‑ready GDSII — every step, every tool stage, every closure decision.\r\nDrive floorplanning, placement, clock tree synthesis, and routing on a non‑CMOS PDK where the standard‑cell shortcuts do not apply by default.\r\nClose timing — setup, hold, and the complex multi‑corner cases — and diagnose where violations actually come from, not just where the report points.\r\nDesign and verify the power grid and run IR drop analysis appropriate to a superconducting current distribution that does not behave like CMOS.\r\nDrive DRC and LVS clean‑up and the physical verification flow through to clean tape‑out conditions.\r\nPartner with the Sign‑off Engineer on final extraction, parasitic data, and the signoff checks that gate tape‑out.\r\nBuild and own the implementation flow itself: TCL, Python, recipe management, and the automation that turns a one‑off block run into a repeatable production flow.\r\nSet the implementation methodology and QoR standards at Snowcap — what a clean place‑and‑route database looks like, what closure means here, and what the next implementation engineer inherits.\r\nWhat We Need to SeeTrack record of running the full digital implementation flow on production silicon — chips that you took from netlist to GDSII and that taped out and ran.\r\nWorking fluency with Synopsys ICC2, Cadence Innovus, or equivalent production place‑and‑route platforms. Not a tool‑evaluation level. Production level.\r\nStrong timing closure skills: setup and hold debug at scale, multi‑corner multi‑mode analysis, and the judgment to choose between RTL changes, floorplan changes, and CTS changes when a path will not close.\r\nSolid working knowledge of power grid design, IR drop analysis, and the implementation decisions that determine sign‑off outcomes downstream.\r\nComfort with custom and semi‑custom flows — not just driving standard‑cell autopilot on a mature PDK with prebuilt scripts.\r\nScripting fluency in TCL and Python — enough to automate flows, build recipes, and customize the implementation environment yourself.\r\nWays to Stand OutHands‑on experience with a NbTiN, NbN, or other non‑CMOS PDK at the implementation level — anything that proves you have closed timing on a logic family that did not behave like CMOS. Very strong differentiator.\r\nPhysical design background at NVIDIA, Intel, Qualcomm, IBM semiconductor, or comparable groups, in the senior or principal physical design band, with shipped silicon to point to.\r\nExperience standing up an implementation flow from zero — first script, first floorplan, first recipe — not just inheriting one.\r\nDeep understanding of the interdependency between implementation choices and sign‑off — STA corners, extraction, EM/IR, DFT, and where the tradeoffs actually live.\r\nMixed‑signal, RF, or custom‑block integration experience inside an otherwise digital flow.\r\nAuthored automation, methodology, or internal IP that other implementation teams have adopted.\r\nFamiliarity with superconducting digital logic — PCL, SFQ, AQFP, RSFQ, or related — at any level. We do not require it; we will weight it heavily when we find it.\r\nThe EnvironmentSnowcap is a small, technically elite team running implementation on a PDK that has no decades of accumulated flow scripts behind it. The standard‑cell autopilot, the inherited methodology, the senior implementation lead who has done this exact node before — none of that is sitting next to you. You will write the flow as you go, and the next implementation engineer to join builds on it.\r\nWe are a flat, matrixed organization. You will work daily with RTL design, design verification, the sign‑off engineer, and the physics team — directly, without layers. When timing will not close and the question is whether it is RTL, floorplan, or PDK, that conversation happens in the room that day, not three weeks from now.\r\nThis role is on‑site at our San Francisco Bay Area or Jacksonville Metro location. The work is hands‑on at the place‑and‑route tool, in timing reports, in TCL, and in the physical verification queue. If you need a mature implementation organization with inherited scripts and a CAD support team standing behind you, this is not the right fit. If you have wanted to define what those scripts and that methodology look like, you are in the right place.\r\nWhy SnowcapSnowcap Compute is building the world’s first commercial superconducting digital computer. Our chips operate at 4.5 Kelvin on Josephson junction‑based PCL logic, consuming a fraction of the power of any CMOS system. We are not improving the existing paradigm — we are replacing it.\r\nWe are a technically elite, small team at the intersection of quantum physics, cryogenic engineering, and advanced semiconductor manufacturing. Every person on this team has a direct line of sight to the product. The work you do here will be visible, consequential, and unprecedented.\r\nThis is the founding implementation seat on the digital side. The flow, the scripts, and the closure methodology you build become the baseline every future block routes through, and the physical artifact you produce is what Snowcap actually tapes out.\r\nCompensationFull medical, dental, and vision\r\n401(k)\r\nRelocation assistance available for candidates outside the area.\r\nBase salary range is shown in USD, posted in good faith and in compliance with California pay transparency law (SB 1162). The range spans the L1 (new grad) entry floor through the senior individual‑contributor band — the offer Snowcap reasonably expects to make depends on the level of the seat being filled, plus experience, skills, and location. Range is exclusive of equity, bonus, and benefits. Range reflects the San Francisco Bay Area market; offers for the same role based in Jacksonville Metro, FL are typically 15–25% lower in line with local market norms.\r\nBased in the San Francisco Bay Area or Jacksonville Metro, FL. On‑Site.#J-18808-Ljbffr","company":"Snowcap Compute","rawCompany":"snowcap compute","city":"Millbrae","state":"CA","isRemote":false,"isActive":true,"createdAt":"2026-11-04T02:37:23.158Z","occupations":[{"code":"17-2072.00","title":"Electronics Engineers, Except Computer","slug":"electronics-engineers-except-computer"},{"code":"17-2061.00","title":"Computer Hardware Engineers","slug":"computer-hardware-engineers"},{"code":"17-2199.00","title":"Engineers, All Other","slug":"engineers-all-other"}],"industries":[{"code":"334413","title":"Semiconductor and Related Device Manufacturing","slug":"semiconductor-and-related-device-manufacturing"},{"code":"334419","title":"Other Electronic Component Manufacturing","slug":"other-electronic-component-manufacturing"},{"code":"334418","title":"Printed Circuit Assembly (Electronic Assembly) Manufacturing","slug":"printed-circuit-assembly-electronic-assembly-manufacturing"}],"jobPosting":{"@context":"https://schema.org","@type":"JobPosting","title":"Digital Implementation Engineer","description":"About the RoleThe chip program runs the standard sequence — architecture, microarchitecture, RTL, verification, implementation, sign-off — and implementation is where the design becomes physically realizable or it does not.\r\nThis is not a standard‑cell autopilot job.\r\nYou will own the digital implementation flow end to end: synthesis through floorplanning, placement, clock tree synthesis, routing, power grid design and IR analysis, and timing closure to tape‑out‑ready GDSII. You will work directly with RTL design, design verification, and the sign‑off engineer in a flat, matrixed organization. When the tool flow does not have the script you need, you will write it. When timing will not close the way the textbook says it should, you will figure out which assumption failed and produce the flow that does close.\r\nIn twelve months, the implementation flow you stand up should be the one every block routes through and the one every sign‑off engineer trusts the inputs from. The scripts, recipes, and methodology you write become the baseline every future implementation engineer at Snowcap inherits.\r\nWhat You'll OwnOwn the physical implementation of digital logic from synthesized netlist through tape‑out‑ready GDSII — every step, every tool stage, every closure decision.\r\nDrive floorplanning, placement, clock tree synthesis, and routing on a non‑CMOS PDK where the standard‑cell shortcuts do not apply by default.\r\nClose timing — setup, hold, and the complex multi‑corner cases — and diagnose where violations actually come from, not just where the report points.\r\nDesign and verify the power grid and run IR drop analysis appropriate to a superconducting current distribution that does not behave like CMOS.\r\nDrive DRC and LVS clean‑up and the physical verification flow through to clean tape‑out conditions.\r\nPartner with the Sign‑off Engineer on final extraction, parasitic data, and the signoff checks that gate tape‑out.\r\nBuild and own the implementation flow itself: TCL, Python, recipe management, and the automation that turns a one‑off block run into a repeatable production flow.\r\nSet the implementation methodology and QoR standards at Snowcap — what a clean place‑and‑route database looks like, what closure means here, and what the next implementation engineer inherits.\r\nWhat We Need to SeeTrack record of running the full digital implementation flow on production silicon — chips that you took from netlist to GDSII and that taped out and ran.\r\nWorking fluency with Synopsys ICC2, Cadence Innovus, or equivalent production place‑and‑route platforms. Not a tool‑evaluation level. Production level.\r\nStrong timing closure skills: setup and hold debug at scale, multi‑corner multi‑mode analysis, and the judgment to choose between RTL changes, floorplan changes, and CTS changes when a path will not close.\r\nSolid working knowledge of power grid design, IR drop analysis, and the implementation decisions that determine sign‑off outcomes downstream.\r\nComfort with custom and semi‑custom flows — not just driving standard‑cell autopilot on a mature PDK with prebuilt scripts.\r\nScripting fluency in TCL and Python — enough to automate flows, build recipes, and customize the implementation environment yourself.\r\nWays to Stand OutHands‑on experience with a NbTiN, NbN, or other non‑CMOS PDK at the implementation level — anything that proves you have closed timing on a logic family that did not behave like CMOS. Very strong differentiator.\r\nPhysical design background at NVIDIA, Intel, Qualcomm, IBM semiconductor, or comparable groups, in the senior or principal physical design band, with shipped silicon to point to.\r\nExperience standing up an implementation flow from zero — first script, first floorplan, first recipe — not just inheriting one.\r\nDeep understanding of the interdependency between implementation choices and sign‑off — STA corners, extraction, EM/IR, DFT, and where the tradeoffs actually live.\r\nMixed‑signal, RF, or custom‑block integration experience inside an otherwise digital flow.\r\nAuthored automation, methodology, or internal IP that other implementation teams have adopted.\r\nFamiliarity with superconducting digital logic — PCL, SFQ, AQFP, RSFQ, or related — at any level. We do not require it; we will weight it heavily when we find it.\r\nThe EnvironmentSnowcap is a small, technically elite team running implementation on a PDK that has no decades of accumulated flow scripts behind it. The standard‑cell autopilot, the inherited methodology, the senior implementation lead who has done this exact node before — none of that is sitting next to you. You will write the flow as you go, and the next implementation engineer to join builds on it.\r\nWe are a flat, matrixed organization. You will work daily with RTL design, design verification, the sign‑off engineer, and the physics team — directly, without layers. When timing will not close and the question is whether it is RTL, floorplan, or PDK, that conversation happens in the room that day, not three weeks from now.\r\nThis role is on‑site at our San Francisco Bay Area or Jacksonville Metro location. The work is hands‑on at the place‑and‑route tool, in timing reports, in TCL, and in the physical verification queue. If you need a mature implementation organization with inherited scripts and a CAD support team standing behind you, this is not the right fit. If you have wanted to define what those scripts and that methodology look like, you are in the right place.\r\nWhy SnowcapSnowcap Compute is building the world’s first commercial superconducting digital computer. Our chips operate at 4.5 Kelvin on Josephson junction‑based PCL logic, consuming a fraction of the power of any CMOS system. We are not improving the existing paradigm — we are replacing it.\r\nWe are a technically elite, small team at the intersection of quantum physics, cryogenic engineering, and advanced semiconductor manufacturing. Every person on this team has a direct line of sight to the product. The work you do here will be visible, consequential, and unprecedented.\r\nThis is the founding implementation seat on the digital side. The flow, the scripts, and the closure methodology you build become the baseline every future block routes through, and the physical artifact you produce is what Snowcap actually tapes out.\r\nCompensationFull medical, dental, and vision\r\n401(k)\r\nRelocation assistance available for candidates outside the area.\r\nBase salary range is shown in USD, posted in good faith and in compliance with California pay transparency law (SB 1162). The range spans the L1 (new grad) entry floor through the senior individual‑contributor band — the offer Snowcap reasonably expects to make depends on the level of the seat being filled, plus experience, skills, and location. Range is exclusive of equity, bonus, and benefits. Range reflects the San Francisco Bay Area market; offers for the same role based in Jacksonville Metro, FL are typically 15–25% lower in line with local market norms.\r\nBased in the San Francisco Bay Area or Jacksonville Metro, FL. On‑Site.#J-18808-Ljbffr","datePosted":"2026-11-04T02:37:23.158Z","dateModified":"2026-11-04T02:37:23.158Z","hiringOrganization":{"@type":"Organization","name":"Snowcap Compute","sameAs":"https://jobsearcher.com"},"jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Millbrae","addressRegion":"CA","addressCountry":"US"}},"identifier":{"@type":"PropertyValue","name":"JobSearcher","value":"b521d315074ca905cace7cf9"},"url":"https://jobsearcher.com/jobs/b521d315074ca905cace7cf9"}}