{"schemaVersion":"jobsearcher.job.v1","id":"b3d3dddaa9c97e0237603c24","url":"https://jobsearcher.com/jobs/b3d3dddaa9c97e0237603c24","canonicalUrl":"https://jobsearcher.com/jobs/b3d3dddaa9c97e0237603c24","title":"Design Engineer","description":"Digital Design Engineer IILocation: Remote but preferred Burlingame, CA – Hybrid roleDuration: 8+ monthsAbout the RoleWe are seeking an experienced Digital Design Engineer II to support the integration of a camera ingest path into an Image Signal Processing (ISP) pipeline. The engineer will work with MIPI C-PHY/D-PHY, CSI-2 receivers, ISP interfaces, and SoC/subsystem integration, while developing the RTL glue logic required to connect these components.The ideal candidate will have strong hands-on experience with Verilog/SystemVerilog, digital microarchitecture, MIPI/CSI-2, camera systems, Python scripting, and SoC integration.Key ResponsibilitiesIntegrate MIPI C-PHY/D-PHY, CSI-2 controller, and ISP IPs at subsystem and chip level.Design and develop RTL glue/bridge logic between CSI-2 and ISP interfaces.Handle stream and virtual-channel processing, data-type unpacking, line/frame framing, pixel packing, width conversion, CDC, backpressure, FIFO/buffering, and error handling.Develop and maintain subsystem microarchitecture and top-level RTL.Define register maps and configuration/control paths using APB, AHB, and AXI.Support subsystem/chip-level integration and contribute to verification planning using Design-for-Verification principles.Maintain Python-based integration and generation tools, including connectivity, register generation, IP assembly, and collateral checks.Support RTL-to-GDS activities, including constraints, synthesis, timing closure, and UPF-based low-power intent.Collaborate with FPGA engineers on early prototyping and validation teams during chip bring-up.Support block handoff and integration into the larger SoC environment.Must-Have Skills4+ years of Digital Design Engineering experience with SoC/subsystem integration ownership.Hands-on experience with MIPI C-PHY and/or D-PHY.Strong understanding of the CSI-2 protocol and camera ISP pipelines.Strong Verilog/System Verilog RTL coding skills.Experience developing new glue/bridge RTL, including CDC, flow control, and Datapath packing.Strong digital microarchitecture experience.Python scripting experience.TCL scripting experience.Familiarity with synthesis and static timing analysis.Experience with UPF-based simulation and low-power design flows.Exposure to System Verilog UVM/OVM.Knowledge or professional experience working with camera systems.Familiarity with AI-assisted coding/tools.Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience.Nice-to-Have SkillsMIPI DSI/display experience.PCIe, USB, or other high-speed interface experience.ISP algorithm/pipeline analysis.Fixed-point Datapath experience.PHY/controller IP vendor deliverable bring-up.PPI/lane-management debugging.DFT/testability and test-program definition.Power-Aware GLS.FPGA prototyping.Tensilica DSP/TIE experience.MSEE or advanced degree in Computer Science.","company":"BCforward","rawCompany":"bcforward","city":"Denver","state":"CO","isRemote":false,"isActive":false,"createdAt":"2026-09-15T08:31:58.991Z","occupations":[{"code":"17-2072.00","title":"Electronics Engineers, Except Computer","slug":"electronics-engineers-except-computer"},{"code":"17-2061.00","title":"Computer Hardware Engineers","slug":"computer-hardware-engineers"},{"code":"15-1299.08","title":"Computer Systems Engineers/Architects","slug":"computer-systems-engineers-architects"}],"industries":[{"code":"334419","title":"Other Electronic Component Manufacturing","slug":"other-electronic-component-manufacturing"},{"code":"541512","title":"Computer Systems Design Services","slug":"computer-systems-design-services"},{"code":"334413","title":"Semiconductor and Related Device Manufacturing","slug":"semiconductor-and-related-device-manufacturing"}],"jobPosting":{"@context":"https://schema.org","@type":"JobPosting","title":"Design Engineer","description":"Digital Design Engineer IILocation: Remote but preferred Burlingame, CA – Hybrid roleDuration: 8+ monthsAbout the RoleWe are seeking an experienced Digital Design Engineer II to support the integration of a camera ingest path into an Image Signal Processing (ISP) pipeline. The engineer will work with MIPI C-PHY/D-PHY, CSI-2 receivers, ISP interfaces, and SoC/subsystem integration, while developing the RTL glue logic required to connect these components.The ideal candidate will have strong hands-on experience with Verilog/SystemVerilog, digital microarchitecture, MIPI/CSI-2, camera systems, Python scripting, and SoC integration.Key ResponsibilitiesIntegrate MIPI C-PHY/D-PHY, CSI-2 controller, and ISP IPs at subsystem and chip level.Design and develop RTL glue/bridge logic between CSI-2 and ISP interfaces.Handle stream and virtual-channel processing, data-type unpacking, line/frame framing, pixel packing, width conversion, CDC, backpressure, FIFO/buffering, and error handling.Develop and maintain subsystem microarchitecture and top-level RTL.Define register maps and configuration/control paths using APB, AHB, and AXI.Support subsystem/chip-level integration and contribute to verification planning using Design-for-Verification principles.Maintain Python-based integration and generation tools, including connectivity, register generation, IP assembly, and collateral checks.Support RTL-to-GDS activities, including constraints, synthesis, timing closure, and UPF-based low-power intent.Collaborate with FPGA engineers on early prototyping and validation teams during chip bring-up.Support block handoff and integration into the larger SoC environment.Must-Have Skills4+ years of Digital Design Engineering experience with SoC/subsystem integration ownership.Hands-on experience with MIPI C-PHY and/or D-PHY.Strong understanding of the CSI-2 protocol and camera ISP pipelines.Strong Verilog/System Verilog RTL coding skills.Experience developing new glue/bridge RTL, including CDC, flow control, and Datapath packing.Strong digital microarchitecture experience.Python scripting experience.TCL scripting experience.Familiarity with synthesis and static timing analysis.Experience with UPF-based simulation and low-power design flows.Exposure to System Verilog UVM/OVM.Knowledge or professional experience working with camera systems.Familiarity with AI-assisted coding/tools.Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience.Nice-to-Have SkillsMIPI DSI/display experience.PCIe, USB, or other high-speed interface experience.ISP algorithm/pipeline analysis.Fixed-point Datapath experience.PHY/controller IP vendor deliverable bring-up.PPI/lane-management debugging.DFT/testability and test-program definition.Power-Aware GLS.FPGA prototyping.Tensilica DSP/TIE experience.MSEE or advanced degree in Computer Science.","datePosted":"2026-09-15T08:31:58.991Z","dateModified":"2026-09-15T08:31:58.991Z","hiringOrganization":{"@type":"Organization","name":"BCforward","sameAs":"https://jobsearcher.com"},"jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Denver","addressRegion":"CO","addressCountry":"US"}},"identifier":{"@type":"PropertyValue","name":"JobSearcher","value":"b3d3dddaa9c97e0237603c24"},"url":"https://jobsearcher.com/jobs/b3d3dddaa9c97e0237603c24"}}