{"schemaVersion":"jobsearcher.job.v1","id":"b1db143476dc09313d2303d9","url":"https://jobsearcher.com/jobs/b1db143476dc09313d2303d9","canonicalUrl":"https://jobsearcher.com/jobs/b1db143476dc09313d2303d9","title":"RFIC Layout Manager","description":"Responsibilities We are seeking an experienced and accomplished Senior Manager – RFIC Layout to lead and drive layout development for complex RF/Analog ICs. This role requires strong technical expertise, proven leadership capabilities, and the ability to manage large teams while owning end-to-end layout delivery across product lines. The ideal candidate will play a critical role in mentoring teams, enabling advanced technology adoption, and ensuring high-quality execution in a cross-functional environment.\r\nLead and manage RF/Analog layout teams, ensuring high-quality and timely delivery of design projects\r\nOwn end-to-end layout development across product lines with strong accountability\r\nMentor, train, and scale teams including freshers and contractors\r\nDrive floor-planning for complex RF/Analog chips and IPs considering noise and isolation constraints\r\nProvide technical leadership in RF signal path and high-speed design implementations\r\nCollaborate with cross-functional teams including ASIC, PnR, CAD, and Packaging\r\nEnsure compliance with Analog IP deliverables, QC processes, and release flows\r\nEnable team readiness for advanced technology nodes and evolving design challenges\r\nQualifications Tech/B.E. with 20+ years of experience in RF/Analog layout.\r\nExperience in managing/mentoring large teams consisting of 20+ members\r\nStrong communication skills with proven track record of owning layout development from product lines.\r\nStrong Technical mentorship skills, Ability to hire/train teams train including freshers/contractors\r\nShould have floor-planning experience for Complex RF/Analog chips & IPs which may need magnetic coupling isolation constraints and noise isolation constraints.\r\nExperience in handling chipsets/top-levels in Wireless/Wi-Fi transceivers and proficiency with RF signal path building blocks such as LNA, mixers, RFPLLs, PA, Multi-GHz ADCs and DACs would be added advantage.\r\nExperience with High speed Serdes Designs (PAM4, PCIe, etc.) and hands on experience in building blocks of Serdes (CTLE, ADCs, DACS, PLL, High speed Clock distribution, etc.).\r\nGood exposure to Fin-FET technology challenges (5nm, 3nm) and should be able to ramp up the team on new technology nodes.\r\nShould have a good overview of the Deliverables/QC of an Analog IP into SoC context and release flows.\r\nShould have good cross-functional knowledge/deliverables with other teams such as ASIC, PnR, CAD and Packaging teams.\r\nKnowledge in ESD/IO design will be added advantage\r\nJ-18808-Ljbffr","company":"Maxlinear","rawCompany":"maxlinear","city":"Irvine","state":"CA","isRemote":false,"isActive":false,"createdAt":"2026-06-19T01:11:15.090Z","occupations":[{"code":"17-2072.00","title":"Electronics Engineers, Except Computer","slug":"electronics-engineers-except-computer"},{"code":"11-9041.00","title":"Architectural and Engineering Managers","slug":"architectural-and-engineering-managers"},{"code":"17-2072.01","title":"Radio Frequency Identification Device Specialists","slug":"radio-frequency-identification-device-specialists"}],"industries":[{"code":"334419","title":"Other Electronic Component Manufacturing","slug":"other-electronic-component-manufacturing"},{"code":"334413","title":"Semiconductor and Related Device Manufacturing","slug":"semiconductor-and-related-device-manufacturing"},{"code":"334418","title":"Printed Circuit Assembly (Electronic Assembly) Manufacturing","slug":"printed-circuit-assembly-electronic-assembly-manufacturing"}],"jobPosting":{"@context":"https://schema.org","@type":"JobPosting","title":"RFIC Layout Manager","description":"Responsibilities We are seeking an experienced and accomplished Senior Manager – RFIC Layout to lead and drive layout development for complex RF/Analog ICs. This role requires strong technical expertise, proven leadership capabilities, and the ability to manage large teams while owning end-to-end layout delivery across product lines. The ideal candidate will play a critical role in mentoring teams, enabling advanced technology adoption, and ensuring high-quality execution in a cross-functional environment.\r\nLead and manage RF/Analog layout teams, ensuring high-quality and timely delivery of design projects\r\nOwn end-to-end layout development across product lines with strong accountability\r\nMentor, train, and scale teams including freshers and contractors\r\nDrive floor-planning for complex RF/Analog chips and IPs considering noise and isolation constraints\r\nProvide technical leadership in RF signal path and high-speed design implementations\r\nCollaborate with cross-functional teams including ASIC, PnR, CAD, and Packaging\r\nEnsure compliance with Analog IP deliverables, QC processes, and release flows\r\nEnable team readiness for advanced technology nodes and evolving design challenges\r\nQualifications Tech/B.E. with 20+ years of experience in RF/Analog layout.\r\nExperience in managing/mentoring large teams consisting of 20+ members\r\nStrong communication skills with proven track record of owning layout development from product lines.\r\nStrong Technical mentorship skills, Ability to hire/train teams train including freshers/contractors\r\nShould have floor-planning experience for Complex RF/Analog chips & IPs which may need magnetic coupling isolation constraints and noise isolation constraints.\r\nExperience in handling chipsets/top-levels in Wireless/Wi-Fi transceivers and proficiency with RF signal path building blocks such as LNA, mixers, RFPLLs, PA, Multi-GHz ADCs and DACs would be added advantage.\r\nExperience with High speed Serdes Designs (PAM4, PCIe, etc.) and hands on experience in building blocks of Serdes (CTLE, ADCs, DACS, PLL, High speed Clock distribution, etc.).\r\nGood exposure to Fin-FET technology challenges (5nm, 3nm) and should be able to ramp up the team on new technology nodes.\r\nShould have a good overview of the Deliverables/QC of an Analog IP into SoC context and release flows.\r\nShould have good cross-functional knowledge/deliverables with other teams such as ASIC, PnR, CAD and Packaging teams.\r\nKnowledge in ESD/IO design will be added advantage\r\nJ-18808-Ljbffr","datePosted":"2026-06-19T01:11:15.090Z","dateModified":"2026-06-19T01:11:15.090Z","hiringOrganization":{"@type":"Organization","name":"Maxlinear","sameAs":"https://jobsearcher.com"},"jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Irvine","addressRegion":"CA","addressCountry":"US"}},"identifier":{"@type":"PropertyValue","name":"JobSearcher","value":"b1db143476dc09313d2303d9"},"url":"https://jobsearcher.com/jobs/b1db143476dc09313d2303d9"}}