{"schemaVersion":"jobsearcher.job.v1","id":"b083ccd454ebdd4fd5a422af","url":"https://jobsearcher.com/jobs/b083ccd454ebdd4fd5a422af","canonicalUrl":"https://jobsearcher.com/jobs/b083ccd454ebdd4fd5a422af","title":"Process Technology Design Engineer","description":"Job Description\nThis position is with the Library Benchmarking team within Intel Foundry's Advanced Design Library organization. The group works closely with both process and product design teams to deliver capabilities that optimize and integrate digital‑logic circuits with Intel’s leading‑edge process technology.\n\nThe successful candidate will participate in the design, development, and analysis of pre‑silicon and post‑silicon \"technology benchmarking metrics.\" These metrics target and benchmark digital‑logic power and performance across the various technology nodes and are used to analyze power/performance trade‑offs between the different Standard Cell library offerings during technology pathfinding.\n\nResponsibilities\n\nParticipate in technology and standard cell library architecture pathfinding activities.\n\nContribute to Design Technology Co‑optimization (DTCO) of different standard cell library offerings on a given technology node.\n\nDesign and develop pre‑silicon and post‑silicon technology benchmarking metrics.\n\nDesign and characterize process monitoring oscillators followed by post‑silicon analysis to identify and quantify FEOL/BEOL factors contributing to the silicon‑to‑simulation gap.\n\nStrong customer orientation, excellent written and verbal communication skills, and the ability to work with external and internal partners in a flexible manner are expected.\n\nQualifications\nMinimum Qualifications\n\nMaster’s degree in Electrical/Computer Engineering with 2+ years of experience – OR – PhD degree in Electrical/Computer Engineering.\n\nTechnical background in CMOS device electronics and digital‑logic/mixed‑signal circuits.\n\nPreferred Qualifications\n\nExperience using CAD tools in one or more of: circuit simulation and modeling, physical layout design, design validation, field solver simulation, design synthesis and APR.\n\nStrong capability in one or more languages (C/C++, TCL, Perl, Python) for design automation.\n\nJMP analysis skills.\n\n2–4 years of working in an industrial environment.\n\nBenefits\nWe offer a total compensation package that ranks among the best in the industry. It includes competitive pay, stock bonuses, and benefit programs that cover health, retirement, and vacation. Annual salary range for US locations is $122,440.00 – $232,190.00 USD.\n\nEmployment Information\n\nJob Type: Experienced Hire\n\nShift: Shift 1 (United States of America)\n\nPrimary Location: US, Oregon, Hillsboro\n\nAdditional Locations: US, Arizona, Phoenix; US, California, Santa Clara; US, Texas, Austin\n\nEEO Statement\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\n\n#J-18808-Ljbffr","company":"SupportFinity","rawCompany":"supportfinity","city":"Hillsboro","state":"IL","isRemote":false,"isActive":false,"createdAt":"2026-06-18T03:23:45.289Z","occupations":[{"code":"17-2072.00","title":"Electronics Engineers, Except Computer","slug":"electronics-engineers-except-computer"},{"code":"17-2199.00","title":"Engineers, All Other","slug":"engineers-all-other"},{"code":"17-2061.00","title":"Computer Hardware Engineers","slug":"computer-hardware-engineers"}],"industries":[{"code":"334413","title":"Semiconductor and Related Device Manufacturing","slug":"semiconductor-and-related-device-manufacturing"},{"code":"334419","title":"Other Electronic Component Manufacturing","slug":"other-electronic-component-manufacturing"},{"code":"334418","title":"Printed Circuit Assembly (Electronic Assembly) Manufacturing","slug":"printed-circuit-assembly-electronic-assembly-manufacturing"}],"jobPosting":{"@context":"https://schema.org","@type":"JobPosting","title":"Process Technology Design Engineer","description":"Job Description\nThis position is with the Library Benchmarking team within Intel Foundry's Advanced Design Library organization. The group works closely with both process and product design teams to deliver capabilities that optimize and integrate digital‑logic circuits with Intel’s leading‑edge process technology.\n\nThe successful candidate will participate in the design, development, and analysis of pre‑silicon and post‑silicon \"technology benchmarking metrics.\" These metrics target and benchmark digital‑logic power and performance across the various technology nodes and are used to analyze power/performance trade‑offs between the different Standard Cell library offerings during technology pathfinding.\n\nResponsibilities\n\nParticipate in technology and standard cell library architecture pathfinding activities.\n\nContribute to Design Technology Co‑optimization (DTCO) of different standard cell library offerings on a given technology node.\n\nDesign and develop pre‑silicon and post‑silicon technology benchmarking metrics.\n\nDesign and characterize process monitoring oscillators followed by post‑silicon analysis to identify and quantify FEOL/BEOL factors contributing to the silicon‑to‑simulation gap.\n\nStrong customer orientation, excellent written and verbal communication skills, and the ability to work with external and internal partners in a flexible manner are expected.\n\nQualifications\nMinimum Qualifications\n\nMaster’s degree in Electrical/Computer Engineering with 2+ years of experience – OR – PhD degree in Electrical/Computer Engineering.\n\nTechnical background in CMOS device electronics and digital‑logic/mixed‑signal circuits.\n\nPreferred Qualifications\n\nExperience using CAD tools in one or more of: circuit simulation and modeling, physical layout design, design validation, field solver simulation, design synthesis and APR.\n\nStrong capability in one or more languages (C/C++, TCL, Perl, Python) for design automation.\n\nJMP analysis skills.\n\n2–4 years of working in an industrial environment.\n\nBenefits\nWe offer a total compensation package that ranks among the best in the industry. It includes competitive pay, stock bonuses, and benefit programs that cover health, retirement, and vacation. Annual salary range for US locations is $122,440.00 – $232,190.00 USD.\n\nEmployment Information\n\nJob Type: Experienced Hire\n\nShift: Shift 1 (United States of America)\n\nPrimary Location: US, Oregon, Hillsboro\n\nAdditional Locations: US, Arizona, Phoenix; US, California, Santa Clara; US, Texas, Austin\n\nEEO Statement\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\n\n#J-18808-Ljbffr","datePosted":"2026-06-18T03:23:45.289Z","dateModified":"2026-06-18T03:23:45.289Z","hiringOrganization":{"@type":"Organization","name":"SupportFinity","sameAs":"https://jobsearcher.com"},"jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Hillsboro","addressRegion":"IL","addressCountry":"US"}},"identifier":{"@type":"PropertyValue","name":"JobSearcher","value":"b083ccd454ebdd4fd5a422af"},"url":"https://jobsearcher.com/jobs/b083ccd454ebdd4fd5a422af"}}