{"schemaVersion":"jobsearcher.job.v1","id":"ae9e129e08a73a6578a4ff6f","url":"https://jobsearcher.com/jobs/ae9e129e08a73a6578a4ff6f","canonicalUrl":"https://jobsearcher.com/jobs/ae9e129e08a73a6578a4ff6f","title":"Collateral Device Engineer","description":"Job Details\r\nJob Description\r\nAbout MDCE\r\nManufacturing Development and Customer Engineering (MDCE) organization serves as the bridge between advanced technology development and practical, scalable manufacturing, ensuring that innovative solutions can be successfully produced and delivered to foundry customers. MDCE Device org is seeking a highly skilled and experienced device technologist with expertise in device collateral development and design rule implementation for foundry technology development.\r\nPosition Overview\r\nAs a device technologist, you will be responsible for developing device collateral including test chip designs, DTCO, product scribe line layouts, manage OPC/Mask requests and managing design rules and waivers for technologies currently in large volume manufacturing. The role focuses on general-purpose logic CMOS technologies to support a broad spectrum of products and markets including high performance compute, mobile, mixed signal, memory controllers, and other diverse applications.\r\nKey Responsibilities\r\nDesign and develop comprehensive device collateral including test chip architectures and product scribe line layouts to support technology characterization and monitoring\r\nCollaborate with Technology Development teams to establish and refine design rules for newly developed device architectures and customize collateral to meet customer-specific requirements\r\nDevelop and manage design-rule waiver processes, ensuring proper documentation and risk assessment for customer applications\r\nCreate and optimize scribe line monitoring structures for yield enhancement and process control in high-volume manufacturing\r\nWork with manufacturing teams to implement device collateral that meets specifications, yield targets, and provides robust process monitoring capabilities\r\nDrive the development of standardized test chip methodologies and scribe line layouts that are compatible with Intel\\'s existing manufacturing processes and platforms\r\nAnalyze device parametric data from test chips and scribe line structures to drive continuous improvement in device performance and manufacturability\r\nProvide technical guidance on design rule compliance and waiver justifications to cross-functional teams and customers\r\nStay updated with industry trends in device collateral design, test methodologies, and design rule evolution to inform development strategies.\r\nIdeal Candidate Must Demonstrate\r\nExcellent technical problem-solving skills with ability to balance design rule compliance with customer flexibility needs\r\nAbility to work collaboratively in globally diverse, cross-disciplinary teams to develop innovative device collateral solutions\r\nProven track record of delivering device collateral solutions in a fast-paced manufacturing environment\r\nDesire to learn, lead, and influence cross-functional teams in collateral development and design rule optimization\r\nQualifications\r\nMinimum Qualifications\r\nMaster\\'s degree in Electrical Engineering, Physics, or related field with 7+ years of experience in CMOS device engineering with focus on test chip design and device collateral development.\r\nThe Years Of Experience Must Include\r\nDemonstrated expertise in CMOS semiconductor device physics and test chip design for advanced transistor device architecture.\r\nExperience in scribe line layout design and process monitoring structure development.\r\nProficiency in design rule development, validation, and waiver management processes.\r\nStrong understanding of DTCO skills including understanding of SRAM, Standard cells and be the key interface and bridge between Process Integration, Yield, Device and Design.\r\nPreferred Qualifications\r\nPh.D. degree in Electrical Engineering, Physics, or related field with 5+ years of experience in CMOS device engineering and collateral development\r\nDemonstrated experience with design of experiment (DOE) principles applied to device collateral optimization\r\nStrong skills in data analysis, scripting, and statistical techniques for test chip data interpretation.\r\nHands-on experience in advanced node test chip design and scribe line optimization for 3nm-16nm FinFETs and sub 3nm GAA FETs\r\nExperience with design rule checker (DRC) development and physical verification flows\r\nExperience in High-Volume Manufacturing environment with focus on yield monitoring and process control structures\r\nKnowledge of statistical process control (SPC) and advanced data analytics for device collateral optimization\r\nKnowledge of mask generation including Boolean/OPC\r\nJob Type\r\nExperienced Hire\r\nShift\r\nShift 1 (United States of America)\r\nPrimary Location\r\nUS, California, Santa Clara\r\nAdditional Locations\r\nUS, Arizona, Phoenix\r\nUS, Oregon, Hillsboro\r\nBusiness Group\r\nIntel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. We ensure our foundry customers\\' products receive our utmost focus in terms of service, technology enablement and capacity commitments. Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, and assembly/test packages the compute devices to improve the lives of every person on Earth.\r\nPosting Statement\r\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\r\nPosition of Trust\r\nN/A\r\nBenefits\r\nWe offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.\r\nAnnual Salary Range for jobs which could be performed in the US: $190,650.00 - 269,150.00 USD. The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.\r\nWork Model for this Role\r\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.\r\nADDITIONAL INFORMATION\r\nIntel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.\r\nJ-18808-Ljbffr","company":"Intel","rawCompany":"intel","city":"Santa Clara","state":"CA","isRemote":false,"isActive":false,"createdAt":"2026-04-09T08:03:40.683Z","occupations":[{"code":"17-2061.00","title":"Computer Hardware Engineers","slug":"computer-hardware-engineers"},{"code":"17-2072.00","title":"Electronics Engineers, Except Computer","slug":"electronics-engineers-except-computer"},{"code":"17-2199.06","title":"Microsystems Engineers","slug":"microsystems-engineers"}],"industries":[{"code":"334413","title":"Semiconductor and Related Device Manufacturing","slug":"semiconductor-and-related-device-manufacturing"},{"code":"334419","title":"Other Electronic Component Manufacturing","slug":"other-electronic-component-manufacturing"},{"code":"334111","title":"Electronic Computer Manufacturing","slug":"electronic-computer-manufacturing"}],"jobPosting":{"@context":"https://schema.org","@type":"JobPosting","title":"Collateral Device Engineer","description":"Job Details\r\nJob Description\r\nAbout MDCE\r\nManufacturing Development and Customer Engineering (MDCE) organization serves as the bridge between advanced technology development and practical, scalable manufacturing, ensuring that innovative solutions can be successfully produced and delivered to foundry customers. MDCE Device org is seeking a highly skilled and experienced device technologist with expertise in device collateral development and design rule implementation for foundry technology development.\r\nPosition Overview\r\nAs a device technologist, you will be responsible for developing device collateral including test chip designs, DTCO, product scribe line layouts, manage OPC/Mask requests and managing design rules and waivers for technologies currently in large volume manufacturing. The role focuses on general-purpose logic CMOS technologies to support a broad spectrum of products and markets including high performance compute, mobile, mixed signal, memory controllers, and other diverse applications.\r\nKey Responsibilities\r\nDesign and develop comprehensive device collateral including test chip architectures and product scribe line layouts to support technology characterization and monitoring\r\nCollaborate with Technology Development teams to establish and refine design rules for newly developed device architectures and customize collateral to meet customer-specific requirements\r\nDevelop and manage design-rule waiver processes, ensuring proper documentation and risk assessment for customer applications\r\nCreate and optimize scribe line monitoring structures for yield enhancement and process control in high-volume manufacturing\r\nWork with manufacturing teams to implement device collateral that meets specifications, yield targets, and provides robust process monitoring capabilities\r\nDrive the development of standardized test chip methodologies and scribe line layouts that are compatible with Intel\\'s existing manufacturing processes and platforms\r\nAnalyze device parametric data from test chips and scribe line structures to drive continuous improvement in device performance and manufacturability\r\nProvide technical guidance on design rule compliance and waiver justifications to cross-functional teams and customers\r\nStay updated with industry trends in device collateral design, test methodologies, and design rule evolution to inform development strategies.\r\nIdeal Candidate Must Demonstrate\r\nExcellent technical problem-solving skills with ability to balance design rule compliance with customer flexibility needs\r\nAbility to work collaboratively in globally diverse, cross-disciplinary teams to develop innovative device collateral solutions\r\nProven track record of delivering device collateral solutions in a fast-paced manufacturing environment\r\nDesire to learn, lead, and influence cross-functional teams in collateral development and design rule optimization\r\nQualifications\r\nMinimum Qualifications\r\nMaster\\'s degree in Electrical Engineering, Physics, or related field with 7+ years of experience in CMOS device engineering with focus on test chip design and device collateral development.\r\nThe Years Of Experience Must Include\r\nDemonstrated expertise in CMOS semiconductor device physics and test chip design for advanced transistor device architecture.\r\nExperience in scribe line layout design and process monitoring structure development.\r\nProficiency in design rule development, validation, and waiver management processes.\r\nStrong understanding of DTCO skills including understanding of SRAM, Standard cells and be the key interface and bridge between Process Integration, Yield, Device and Design.\r\nPreferred Qualifications\r\nPh.D. degree in Electrical Engineering, Physics, or related field with 5+ years of experience in CMOS device engineering and collateral development\r\nDemonstrated experience with design of experiment (DOE) principles applied to device collateral optimization\r\nStrong skills in data analysis, scripting, and statistical techniques for test chip data interpretation.\r\nHands-on experience in advanced node test chip design and scribe line optimization for 3nm-16nm FinFETs and sub 3nm GAA FETs\r\nExperience with design rule checker (DRC) development and physical verification flows\r\nExperience in High-Volume Manufacturing environment with focus on yield monitoring and process control structures\r\nKnowledge of statistical process control (SPC) and advanced data analytics for device collateral optimization\r\nKnowledge of mask generation including Boolean/OPC\r\nJob Type\r\nExperienced Hire\r\nShift\r\nShift 1 (United States of America)\r\nPrimary Location\r\nUS, California, Santa Clara\r\nAdditional Locations\r\nUS, Arizona, Phoenix\r\nUS, Oregon, Hillsboro\r\nBusiness Group\r\nIntel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. We ensure our foundry customers\\' products receive our utmost focus in terms of service, technology enablement and capacity commitments. Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, and assembly/test packages the compute devices to improve the lives of every person on Earth.\r\nPosting Statement\r\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\r\nPosition of Trust\r\nN/A\r\nBenefits\r\nWe offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.\r\nAnnual Salary Range for jobs which could be performed in the US: $190,650.00 - 269,150.00 USD. The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.\r\nWork Model for this Role\r\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.\r\nADDITIONAL INFORMATION\r\nIntel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.\r\nJ-18808-Ljbffr","datePosted":"2026-04-09T08:03:40.683Z","dateModified":"2026-04-09T08:03:40.683Z","hiringOrganization":{"@type":"Organization","name":"Intel","sameAs":"https://jobsearcher.com"},"jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Santa Clara","addressRegion":"CA","addressCountry":"US"}},"identifier":{"@type":"PropertyValue","name":"JobSearcher","value":"ae9e129e08a73a6578a4ff6f"},"url":"https://jobsearcher.com/jobs/ae9e129e08a73a6578a4ff6f"}}