{"schemaVersion":"jobsearcher.job.v1","id":"acabcce773e4c2419aa662f1","url":"https://jobsearcher.com/jobs/acabcce773e4c2419aa662f1","canonicalUrl":"https://jobsearcher.com/jobs/acabcce773e4c2419aa662f1","title":"Thermal Simulation Engineer","description":"Cspeed IO is a stealth start up backed by Sutter Hill Ventures and Atreides Capital - headquartered in Palo Alto, CA. Our executive team has a demonstrated track record of building and scaling category-defining semiconductor and infrastructure businesses at companies like Broadcom, Lumentum, Tesla, Apple, Samsung, Intel, and VMware.\nCspeed IO is developing next-generation optical semiconductor solutions for the AI infrastructure market, focused on enabling true \"scale-up\" architectures. Our mission is to replace traditional copper interconnects with advanced fiber-optic technologies that overcome the limitations of existing optics solutions and architectures.\nThe Role\nThis position owns thermal modeling for CspeedIO optical engines, from die-level power maps through cooling boundary conditions, and the correlation of those models against measured hardware.\nThermal design here is a functional requirement rather than a reliability margin. Photonic device behavior is temperature-dependent, so wavelength and channel-to-channel uniformity shift with the temperature field across the photonic IC. The assembly also contains a small-footprint, high-flux die whose temperature must be held within a narrow window, and the engine operates adjacent to a host ASIC whose dissipation we do not control. The deliverable is a defensible temperature field, not a junction temperature.\nResponsibilities\nThermal modeling and architecture\n Build and maintain thermal models of the optical engine spanning die, package, interface materials, lid, and cold plate, for air- and liquid-cooled configurations. Establish the cooling boundary condition methodology and its validity limits, and quantify thermal crosstalk from adjacent high-power devices. Resolve the temperature field across the photonic IC to the resolution photonic design requires, and own the resulting gradient and uniformity specifications. \nMaterials and interfaces\n Define the heat extraction path for high-flux die within the assembly, die attach, and thermal interface material selection where footprint and power density are constraining. Quantify the sensitivity of engine temperature to material property tolerance and assembly variation. \nCorrelation and design influence\n Define the thermal characterization plan and lead simulation-to-hardware correlation to a stated and tracked accuracy tolerance.\nProvide thermal requirements and constraints to package layout, photonic design, and electrical design during architecture definition rather than after freeze.\nGenerate reduced-order thermal models for system integrators and customers, and engage cold plate, heat sink, and thermal material suppliers. \nRequired Qualifications\n MS or PhD in Mechanical Engineering, Electrical Engineering, Physics, or equivalent practical background.\n6+ years of thermal simulation for semiconductor packages or electronic systems, including one product carried from architecture through hardware correlation.\nExpert proficiency in a commercial thermal or CFD tool for electronics: Ansys Icepak or Fluent, Simcenter Flotherm, Cadence Celsius, or equivalent.\nCommand of heat transfer fundamentals sufficient to defend a model rather than only to run one.\nDemonstrated correlation of thermal simulation against measured hardware, with methodology revised on that basis. \nPreferred Qualifications\n Silicon photonics or optoelectronic thermal work, particularly thermo-optic sensitivity and wavelength stability.\nThermal design for small-footprint, high-flux die.\nDirect-to-chip liquid cooling and cold plate design or specification.\n5D/3D package thermal modeling, and coupled electrothermal or thermal-structural workflows.\nFirst-generation product experience where the thermal methodology had to be established rather than inherited. \nScope and Impact\nThe temperature field this position defines sets the operating envelope for the photonic IC and the thermally critical die around it, and therefore constrains link budget, tuning power, and achievable channel density. The methodology does not currently exist in a documented, correlated form.\n#J-18808-Ljbffr","company":"Cscale","rawCompany":"cscale","city":"Eastern","state":"KY","isRemote":false,"isActive":false,"createdAt":"2026-10-04T03:30:45.873Z","occupations":[{"code":"17-2199.07","title":"Photonics Engineers","slug":"photonics-engineers"},{"code":"17-2199.00","title":"Engineers, All Other","slug":"engineers-all-other"},{"code":"17-2141.00","title":"Mechanical Engineers","slug":"mechanical-engineers"}],"industries":[{"code":"541715","title":"Research and Development in the Physical, Engineering, and Life Sciences (except Nanotechnology and Biotechnology)","slug":"research-and-development-in-the-physical-engineering-and-life-sciences-except-nanotechnology-and-biotechnology"},{"code":"334413","title":"Semiconductor and Related Device Manufacturing","slug":"semiconductor-and-related-device-manufacturing"},{"code":"334419","title":"Other Electronic Component Manufacturing","slug":"other-electronic-component-manufacturing"}],"jobPosting":{"@context":"https://schema.org","@type":"JobPosting","title":"Thermal Simulation Engineer","description":"Cspeed IO is a stealth start up backed by Sutter Hill Ventures and Atreides Capital - headquartered in Palo Alto, CA. Our executive team has a demonstrated track record of building and scaling category-defining semiconductor and infrastructure businesses at companies like Broadcom, Lumentum, Tesla, Apple, Samsung, Intel, and VMware.\nCspeed IO is developing next-generation optical semiconductor solutions for the AI infrastructure market, focused on enabling true \"scale-up\" architectures. Our mission is to replace traditional copper interconnects with advanced fiber-optic technologies that overcome the limitations of existing optics solutions and architectures.\nThe Role\nThis position owns thermal modeling for CspeedIO optical engines, from die-level power maps through cooling boundary conditions, and the correlation of those models against measured hardware.\nThermal design here is a functional requirement rather than a reliability margin. Photonic device behavior is temperature-dependent, so wavelength and channel-to-channel uniformity shift with the temperature field across the photonic IC. The assembly also contains a small-footprint, high-flux die whose temperature must be held within a narrow window, and the engine operates adjacent to a host ASIC whose dissipation we do not control. The deliverable is a defensible temperature field, not a junction temperature.\nResponsibilities\nThermal modeling and architecture\n Build and maintain thermal models of the optical engine spanning die, package, interface materials, lid, and cold plate, for air- and liquid-cooled configurations. Establish the cooling boundary condition methodology and its validity limits, and quantify thermal crosstalk from adjacent high-power devices. Resolve the temperature field across the photonic IC to the resolution photonic design requires, and own the resulting gradient and uniformity specifications. \nMaterials and interfaces\n Define the heat extraction path for high-flux die within the assembly, die attach, and thermal interface material selection where footprint and power density are constraining. Quantify the sensitivity of engine temperature to material property tolerance and assembly variation. \nCorrelation and design influence\n Define the thermal characterization plan and lead simulation-to-hardware correlation to a stated and tracked accuracy tolerance.\nProvide thermal requirements and constraints to package layout, photonic design, and electrical design during architecture definition rather than after freeze.\nGenerate reduced-order thermal models for system integrators and customers, and engage cold plate, heat sink, and thermal material suppliers. \nRequired Qualifications\n MS or PhD in Mechanical Engineering, Electrical Engineering, Physics, or equivalent practical background.\n6+ years of thermal simulation for semiconductor packages or electronic systems, including one product carried from architecture through hardware correlation.\nExpert proficiency in a commercial thermal or CFD tool for electronics: Ansys Icepak or Fluent, Simcenter Flotherm, Cadence Celsius, or equivalent.\nCommand of heat transfer fundamentals sufficient to defend a model rather than only to run one.\nDemonstrated correlation of thermal simulation against measured hardware, with methodology revised on that basis. \nPreferred Qualifications\n Silicon photonics or optoelectronic thermal work, particularly thermo-optic sensitivity and wavelength stability.\nThermal design for small-footprint, high-flux die.\nDirect-to-chip liquid cooling and cold plate design or specification.\n5D/3D package thermal modeling, and coupled electrothermal or thermal-structural workflows.\nFirst-generation product experience where the thermal methodology had to be established rather than inherited. \nScope and Impact\nThe temperature field this position defines sets the operating envelope for the photonic IC and the thermally critical die around it, and therefore constrains link budget, tuning power, and achievable channel density. The methodology does not currently exist in a documented, correlated form.\n#J-18808-Ljbffr","datePosted":"2026-10-04T03:30:45.873Z","dateModified":"2026-10-04T03:30:45.873Z","hiringOrganization":{"@type":"Organization","name":"Cscale","sameAs":"https://jobsearcher.com"},"jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Eastern","addressRegion":"KY","addressCountry":"US"}},"identifier":{"@type":"PropertyValue","name":"JobSearcher","value":"acabcce773e4c2419aa662f1"},"url":"https://jobsearcher.com/jobs/acabcce773e4c2419aa662f1"}}