{"schemaVersion":"jobsearcher.job.v1","id":"aa92a53563df4cbafd40b17c","url":"https://jobsearcher.com/jobs/aa92a53563df4cbafd40b17c","canonicalUrl":"https://jobsearcher.com/jobs/aa92a53563df4cbafd40b17c","title":"Systems Design Engineer, Digital Signal Processing","description":"Minimum qualifications:\nBachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field.\n10 years of experience in design for Digital Signal Processing (DSP) or high-speed digital logic.\nExperience in Verilog/SystemVerilog or VHDL.\nExperience with MATLAB, Python, or C++ for algorithmic modeling and verification.\n\nPreferred qualifications:\nMaster's degree or PhD in Electrical Engineering, Computer Engineering, or a related technical field.\nExperience taking complex DSP designs through the full front-end flow: Synthesis (Design Compiler/Genus), STA (PrimeTime/Tempus), and CDC/LEC (Spyglass/Conformal).\nExperience implementing digital blocks for Communication Systems or PHY (e.g., filters, interpolators, or equalizers).\nExperience with advanced FinFET process nodes (e.g., 5nm, 3nm) and achieving timing closure at GHz frequencies.\nUnderstanding of low-power design techniques and dynamic power optimization.\nAbout the job\nIn this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.\nAs a Systems Design Engineer, you will be the driving factor behind the physical implementation of next-generation TPU technology. You will own the critical path from mathematical model to bit-exact silicon. Your expertise in front-end design flows will be essential in delivering the hardware that powers Google's advanced AI models and cloud services.\nThe AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.\nWe're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.\nIndividual pay is determined by factors including job-related skills, experience, and relevant education or training.\n\nUS: $192000 - $278000 (USD) + 20% bonus target + equity + benefits\n\nLearn more about benefits at Google.\nResponsibilities\nLead the design and implementation of high-speed blocks. Solve complex implementation issues related to GHz-frequency timing closure and advanced process nodes.\n\nTransform high-level architectural specifications and communication theory models into efficient, bit-exact implementations.\n\nPerform fixed-point analysis and micro-architectural trade-offs to optimize for area, power, and performance.\n\nDrive the front-end design flow to ensure sign-off quality designs.\n\nCollaborate closely with verification teams to develop bit-exact C++/SystemC models.\n\nGoogle is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.","company":"Google","rawCompany":"google","city":"Sunnyvale","state":"CA","isRemote":false,"isActive":false,"createdAt":"2026-07-31T11:11:46.887Z","occupations":[{"code":"17-2072.00","title":"Electronics Engineers, Except Computer","slug":"electronics-engineers-except-computer"},{"code":"17-2199.00","title":"Engineers, All Other","slug":"engineers-all-other"},{"code":"17-2061.00","title":"Computer Hardware Engineers","slug":"computer-hardware-engineers"}],"industries":[{"code":"541512","title":"Computer Systems Design Services","slug":"computer-systems-design-services"},{"code":"334413","title":"Semiconductor and Related Device Manufacturing","slug":"semiconductor-and-related-device-manufacturing"},{"code":"334111","title":"Electronic Computer Manufacturing","slug":"electronic-computer-manufacturing"}],"jobPosting":{"@context":"https://schema.org","@type":"JobPosting","title":"Systems Design Engineer, Digital Signal Processing","description":"Minimum qualifications:\nBachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field.\n10 years of experience in design for Digital Signal Processing (DSP) or high-speed digital logic.\nExperience in Verilog/SystemVerilog or VHDL.\nExperience with MATLAB, Python, or C++ for algorithmic modeling and verification.\n\nPreferred qualifications:\nMaster's degree or PhD in Electrical Engineering, Computer Engineering, or a related technical field.\nExperience taking complex DSP designs through the full front-end flow: Synthesis (Design Compiler/Genus), STA (PrimeTime/Tempus), and CDC/LEC (Spyglass/Conformal).\nExperience implementing digital blocks for Communication Systems or PHY (e.g., filters, interpolators, or equalizers).\nExperience with advanced FinFET process nodes (e.g., 5nm, 3nm) and achieving timing closure at GHz frequencies.\nUnderstanding of low-power design techniques and dynamic power optimization.\nAbout the job\nIn this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.\nAs a Systems Design Engineer, you will be the driving factor behind the physical implementation of next-generation TPU technology. You will own the critical path from mathematical model to bit-exact silicon. Your expertise in front-end design flows will be essential in delivering the hardware that powers Google's advanced AI models and cloud services.\nThe AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.\nWe're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.\nIndividual pay is determined by factors including job-related skills, experience, and relevant education or training.\n\nUS: $192000 - $278000 (USD) + 20% bonus target + equity + benefits\n\nLearn more about benefits at Google.\nResponsibilities\nLead the design and implementation of high-speed blocks. Solve complex implementation issues related to GHz-frequency timing closure and advanced process nodes.\n\nTransform high-level architectural specifications and communication theory models into efficient, bit-exact implementations.\n\nPerform fixed-point analysis and micro-architectural trade-offs to optimize for area, power, and performance.\n\nDrive the front-end design flow to ensure sign-off quality designs.\n\nCollaborate closely with verification teams to develop bit-exact C++/SystemC models.\n\nGoogle is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.","datePosted":"2026-07-31T11:11:46.887Z","dateModified":"2026-07-31T11:11:46.887Z","hiringOrganization":{"@type":"Organization","name":"Google","sameAs":"https://jobsearcher.com"},"jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Sunnyvale","addressRegion":"CA","addressCountry":"US"}},"identifier":{"@type":"PropertyValue","name":"JobSearcher","value":"aa92a53563df4cbafd40b17c"},"url":"https://jobsearcher.com/jobs/aa92a53563df4cbafd40b17c"}}