{"schemaVersion":"jobsearcher.job.v1","id":"a0e02ce8fcbd7d328a8a7a96","url":"https://jobsearcher.com/jobs/a0e02ce8fcbd7d328a8a7a96","canonicalUrl":"https://jobsearcher.com/jobs/a0e02ce8fcbd7d328a8a7a96","title":"Staff Networking/Interoperability Validation Engineer (Switches/NICs/AEC/Transceivers)","description":"About Marvell\n\nMarvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.\n\nAt Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.\n\nYour Team, Your Impact\n\nHigh-speed interconnects — from switch and NIC silicon to optical transceivers and active electrical cables — are what let modern spine-leaf data centers and AI/ML fabrics move data at 800G, 1.6T, and beyond without a hitch. As a member of the Network Validation / Interoperability Testing team, you'll recreate real-world deployment scenarios in the lab and drive failure modes to resolution with design and firmware teams. You will ensure next-generation, ultra-high-speed networking gear from multiple vendors interoperates correctly — spanning everything from PHY-layer signal integrity up through routing protocols — leveraging LLMs and AI agent workflows to do it faster and more efficiently.\n\nWhat You Can Expect\n\nDesign, develop, and execute interoperability test plans for Marvell networking products across a wide range of multi-vendor platforms and customer environments, validating device compatibility against industry-standard switches, NICs, cables, and transceivers through automated test frameworks built for coverage, repeatability, and time-to-data.\nAnalyze test results, identify failure modes, and work cross-functionally with design and firmware teams to drive root cause resolution.\nValidate PHY-layer behavior including SerDes link bring-up, PAM4/NRZ signal integrity, FEC performance, and low-level protocol compliance across I2C, SPI, and SMI interfaces.\nLeverage AI frameworks and LLMs to accelerate data analysis, anomaly detection, and test automation.\nDocument test methodologies, results, and findings in a clear and structured manner for internal and external stakeholders.\nEngage directly with customers and partners to understand interoperability requirements and ensure test coverage reflects real-world deployment scenarios.\nContinuously evaluate and improve test infrastructure to keep pace with next-generation networking technologies.\nAutomation system development using AI agents design tests, improve test efficiency, improve time to data and data analysis.\n\nWhat We're Looking For\n\nMS/PhD (preferred) in CE/EE or related technical field(s) with 1-3+ years of previous experience\nExperience in designing and executing interoperability test plans across multi-vendor networking environments using automated test frameworks, with proficiency in scripting and network CLI commands across switch and NIC platforms\nKnowledgeable in analyzing large volumes of test data in real time, isolating failure modes, and driving root cause resolution cross-functionally with design and firmware teams\nKnowledgeable in PHY-layer validation including SerDes link bring-up, PAM4/NRZ signal integrity, FEC performance, and low-level protocol compliance across I2C, SPI, and SMI interfaces\nKnowledgeable in leveraging LLMs and AI frameworks to accelerate data analysis, anomaly detection, and test automation through AI agent workflows\nKnowledgeable in networking protocols (Ethernet, IP, BGP, OSPF), data center topologies (spine-leaf, fat-tree), OSI model layers, and data communication protocols to produce clear, structured documentation of test methodologies, results, and findings for internal and external stakeholders\nKnowledgeable in translating real-world data center deployment scenarios into interoperability test coverage through direct customer and partner engagement, with understanding of multi-vendor switch and NIC ecosystems\nKnowledgeable in high-speed interconnect standards (800G, 1.6T), data center switching architectures, transceiver and cable specifications, and next-generation networking technologies to continuously evaluate and improve test infrastructure\n\nExpected Base Pay Range (USD)\n\n111,070 - 166,400, $ per annum\n\nThe successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.\n\nThis role is eligible to participate in Marvell's bonus and equity plans, including a new hire equity grant and annual equity refreshers, ensuring you are rewarded for your contributions and remain invested in the company's long-term success.\n\nAdditional Compensation and Benefit Elements\n\nMarvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.\n\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.\n\nAny applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.\n\nInterview Integrity\n\nTo support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.\n\nThese tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.\n\nThis position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.\n\n#LI-AR3","company":"Marvelltechnology1","rawCompany":"marvelltechnology1","city":"San Jose","state":"CA","isRemote":false,"isActive":false,"createdAt":"2026-09-04T11:11:01.815Z","occupations":[{"code":"15-1299.08","title":"Computer Systems Engineers/Architects","slug":"computer-systems-engineers-architects"},{"code":"17-2112.02","title":"Validation Engineers","slug":"validation-engineers"},{"code":"15-1241.00","title":"Computer Network Architects","slug":"computer-network-architects"}],"industries":[{"code":"541512","title":"Computer Systems Design Services","slug":"computer-systems-design-services"},{"code":"541715","title":"Research and Development in the Physical, Engineering, and Life Sciences (except Nanotechnology and Biotechnology)","slug":"research-and-development-in-the-physical-engineering-and-life-sciences-except-nanotechnology-and-biotechnology"},{"code":"541330","title":"Engineering Services","slug":"engineering-services"}],"jobPosting":{"@context":"https://schema.org","@type":"JobPosting","title":"Staff Networking/Interoperability Validation Engineer (Switches/NICs/AEC/Transceivers)","description":"About Marvell\n\nMarvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.\n\nAt Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.\n\nYour Team, Your Impact\n\nHigh-speed interconnects — from switch and NIC silicon to optical transceivers and active electrical cables — are what let modern spine-leaf data centers and AI/ML fabrics move data at 800G, 1.6T, and beyond without a hitch. As a member of the Network Validation / Interoperability Testing team, you'll recreate real-world deployment scenarios in the lab and drive failure modes to resolution with design and firmware teams. You will ensure next-generation, ultra-high-speed networking gear from multiple vendors interoperates correctly — spanning everything from PHY-layer signal integrity up through routing protocols — leveraging LLMs and AI agent workflows to do it faster and more efficiently.\n\nWhat You Can Expect\n\nDesign, develop, and execute interoperability test plans for Marvell networking products across a wide range of multi-vendor platforms and customer environments, validating device compatibility against industry-standard switches, NICs, cables, and transceivers through automated test frameworks built for coverage, repeatability, and time-to-data.\nAnalyze test results, identify failure modes, and work cross-functionally with design and firmware teams to drive root cause resolution.\nValidate PHY-layer behavior including SerDes link bring-up, PAM4/NRZ signal integrity, FEC performance, and low-level protocol compliance across I2C, SPI, and SMI interfaces.\nLeverage AI frameworks and LLMs to accelerate data analysis, anomaly detection, and test automation.\nDocument test methodologies, results, and findings in a clear and structured manner for internal and external stakeholders.\nEngage directly with customers and partners to understand interoperability requirements and ensure test coverage reflects real-world deployment scenarios.\nContinuously evaluate and improve test infrastructure to keep pace with next-generation networking technologies.\nAutomation system development using AI agents design tests, improve test efficiency, improve time to data and data analysis.\n\nWhat We're Looking For\n\nMS/PhD (preferred) in CE/EE or related technical field(s) with 1-3+ years of previous experience\nExperience in designing and executing interoperability test plans across multi-vendor networking environments using automated test frameworks, with proficiency in scripting and network CLI commands across switch and NIC platforms\nKnowledgeable in analyzing large volumes of test data in real time, isolating failure modes, and driving root cause resolution cross-functionally with design and firmware teams\nKnowledgeable in PHY-layer validation including SerDes link bring-up, PAM4/NRZ signal integrity, FEC performance, and low-level protocol compliance across I2C, SPI, and SMI interfaces\nKnowledgeable in leveraging LLMs and AI frameworks to accelerate data analysis, anomaly detection, and test automation through AI agent workflows\nKnowledgeable in networking protocols (Ethernet, IP, BGP, OSPF), data center topologies (spine-leaf, fat-tree), OSI model layers, and data communication protocols to produce clear, structured documentation of test methodologies, results, and findings for internal and external stakeholders\nKnowledgeable in translating real-world data center deployment scenarios into interoperability test coverage through direct customer and partner engagement, with understanding of multi-vendor switch and NIC ecosystems\nKnowledgeable in high-speed interconnect standards (800G, 1.6T), data center switching architectures, transceiver and cable specifications, and next-generation networking technologies to continuously evaluate and improve test infrastructure\n\nExpected Base Pay Range (USD)\n\n111,070 - 166,400, $ per annum\n\nThe successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.\n\nThis role is eligible to participate in Marvell's bonus and equity plans, including a new hire equity grant and annual equity refreshers, ensuring you are rewarded for your contributions and remain invested in the company's long-term success.\n\nAdditional Compensation and Benefit Elements\n\nMarvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.\n\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.\n\nAny applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.\n\nInterview Integrity\n\nTo support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.\n\nThese tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.\n\nThis position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.\n\n#LI-AR3","datePosted":"2026-09-04T11:11:01.815Z","dateModified":"2026-09-04T11:11:01.815Z","hiringOrganization":{"@type":"Organization","name":"Marvelltechnology1","sameAs":"https://jobsearcher.com"},"jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"San Jose","addressRegion":"CA","addressCountry":"US"}},"identifier":{"@type":"PropertyValue","name":"JobSearcher","value":"a0e02ce8fcbd7d328a8a7a96"},"url":"https://jobsearcher.com/jobs/a0e02ce8fcbd7d328a8a7a96"}}