ASIC CAD/EDA Flow/Methodology Developer

Company DescriptionSARACA is a global engineering R&D services company serving over 25 Fortune 500 clients across multiple industries, including MedTech, Aerospace, Automotive, Semiconductor, and Defense. Leveraging expertise in areas like embedded software, UI/UX, mechanical systems, and product testing, SARACA specializes in innovative engineering solutions. As an ISO 13485 certified organization, the company has unique proficiency in global standards such as IEC 62304 and EU MDR. With a skilled team of 400+ engineers and management consultants, SARACA delivers solutions to complex challenges worldwide. Dedicated to fostering a culture of innovation and continuous learning, SARACA is committed to empowering its customers and employees alike.Role: ASIC CAD/EDA Flow/Methodology Developer Work location: Irvine/San Jose (CA) Background and Meet and Greet: MANDATORY Job Description: "• 8+ years of experience in analog/mixed-signal layout design of deep submicron CMOS circuits and at least 3+ years of recent experience on advance nodes including FinFET technologies • Great understanding of CAD flows and tools related to ASIC/SOC methodologies • Excellent programming skills in languages: SKILL, Perl; Python is a plus • Strong fundamentals in software development • Knowledge with EMIR (RV), Physical design verification (DRC/LVS/PEX/ERC), waiver • Working knowledge of circuit design concepts such as device characteristics, SPICE and Verilog netlists and simulation • Excellent communication and interpersonal skills " Key Responsibilities: "• Influence tools, flows, and overall design methodology in design construction, signoff, and optimization with a data driven approach. • Knowledge of signoff closure – Timing with SI and OCV, Power, IR and Physical Verification at both block and chip level • Experience in Block-level and Full-chip integration. • Understanding constraints and fixing design/timing techniques • Interpreting LVS, DRC and ERC reports to find the fastest way to complete layout • Utilizing advanced CAD tools and mask design knowledge to deliver correct and robust layout that meet stringent matching performance, area, and power requirements • Understanding constraints and fixing design/timing techniques • Understanding SI prevention, fixing methodology and implementation • Proficient in Synopsys tools such ICC/ICC2, Cadence Innovus/Virtuoso • Experience in Design Automation and UNIX system. " What are the Mandatory skills and skill proficiencies required for this position? "Python (Preference: 5) Synopsys/Cadence EDA tools/flows (Preference: 5) TCL/Perl (Preference: 5)"