{"schemaVersion":"jobsearcher.job.v1","id":"9643796cd6d5ba5f33b9614a","url":"https://jobsearcher.com/jobs/9643796cd6d5ba5f33b9614a","canonicalUrl":"https://jobsearcher.com/jobs/9643796cd6d5ba5f33b9614a","title":"Sr. DFT Design Engineer, AWS Machine Learning Acceleration","description":"Sr. DFT Design Engineer, AWS Machine Learning Acceleration\nCustom SoCs (System on Chip) are at the heart of AWS Machine Learning servers. As a member of the Cloud‑Scale Machine Learning Acceleration team, you will design and optimize hardware for our data centers, including AWS Inferentia and Trainium servers—our custom‑designed machine‑learning inference and training platforms. Your work will help us drive world‑class server infrastructure, handle massive scale, and integrate emerging technologies.\n\nKey Responsibilities\n\nDefine and develop state‑of‑the‑art Design for Test (DFT) architectures for advanced technology nodes.\n\nCollaborate with block designers and the Physical Design (PD) team to implement highly efficient DFT solutions.\n\nServe as the primary point of contact for cross‑functional stakeholders (PD, Architecture, Product Engineering) to align schedules and goals.\n\nMentor and develop junior engineers through code reviews, methodology training, and technical guidance.\n\nManage project timelines and deliverables, ensuring high‑quality DFT implementation from RTL through silicon bring‑up.\n\nBasic Qualifications\n\nBachelor's degree in computer science, electrical engineering, or a related field.\n\n5+ years of practical semiconductor ASIC design experience, including owning end‑to‑end design of major SOC blocks.\n\nKnowledge of industry‑standard DFT tools and practices (ATPG, JTAG, MBIST) and trade‑offs between test quality and test time.\n\nExperience with automation script development.\n\nPreferred Qualifications\n\nMaster's or Ph.D. degree in Electrical Engineering or a related field.\n\nExperience in RTL coding and debugging, as well as performance, power, area analysis and trade‑offs.\n\nExperience with modern ASIC/FPGA design and verification tools.\n\nExperience with SOC bring‑up and post‑silicon validation.\n\nExperience with gate‑level testing and multi‑clock design practices (CDC).\n\nBroad knowledge of chip design from micro‑architecture through physical design.\n\nKnowledge of design verification (DV) simulation methodologies.\n\nStrong programming and scripting skills in Perl, Python, or Tcl.\n\nExperience with industry standard DFT/SCAN/ATPG tools.\n\nExperience with STA constraints development and analysis for DFT modes.\n\nPractical experience with silicon debug.\n\nAmazon is an equal‑opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status.\n\n#J-18808-Ljbffr","company":"Amazon","rawCompany":"amazon","city":"Austin","state":"TX","isRemote":false,"isActive":true,"createdAt":"2026-06-20T05:00:33.725Z","occupations":[{"code":"17-2072.00","title":"Electronics Engineers, Except Computer","slug":"electronics-engineers-except-computer"},{"code":"17-2061.00","title":"Computer Hardware Engineers","slug":"computer-hardware-engineers"},{"code":"15-1299.08","title":"Computer Systems Engineers/Architects","slug":"computer-systems-engineers-architects"}],"industries":[{"code":"541512","title":"Computer Systems Design Services","slug":"computer-systems-design-services"},{"code":"334413","title":"Semiconductor and Related Device Manufacturing","slug":"semiconductor-and-related-device-manufacturing"},{"code":"334111","title":"Electronic Computer Manufacturing","slug":"electronic-computer-manufacturing"}],"jobPosting":{"@context":"https://schema.org","@type":"JobPosting","title":"Sr. DFT Design Engineer, AWS Machine Learning Acceleration","description":"Sr. DFT Design Engineer, AWS Machine Learning Acceleration\nCustom SoCs (System on Chip) are at the heart of AWS Machine Learning servers. As a member of the Cloud‑Scale Machine Learning Acceleration team, you will design and optimize hardware for our data centers, including AWS Inferentia and Trainium servers—our custom‑designed machine‑learning inference and training platforms. Your work will help us drive world‑class server infrastructure, handle massive scale, and integrate emerging technologies.\n\nKey Responsibilities\n\nDefine and develop state‑of‑the‑art Design for Test (DFT) architectures for advanced technology nodes.\n\nCollaborate with block designers and the Physical Design (PD) team to implement highly efficient DFT solutions.\n\nServe as the primary point of contact for cross‑functional stakeholders (PD, Architecture, Product Engineering) to align schedules and goals.\n\nMentor and develop junior engineers through code reviews, methodology training, and technical guidance.\n\nManage project timelines and deliverables, ensuring high‑quality DFT implementation from RTL through silicon bring‑up.\n\nBasic Qualifications\n\nBachelor's degree in computer science, electrical engineering, or a related field.\n\n5+ years of practical semiconductor ASIC design experience, including owning end‑to‑end design of major SOC blocks.\n\nKnowledge of industry‑standard DFT tools and practices (ATPG, JTAG, MBIST) and trade‑offs between test quality and test time.\n\nExperience with automation script development.\n\nPreferred Qualifications\n\nMaster's or Ph.D. degree in Electrical Engineering or a related field.\n\nExperience in RTL coding and debugging, as well as performance, power, area analysis and trade‑offs.\n\nExperience with modern ASIC/FPGA design and verification tools.\n\nExperience with SOC bring‑up and post‑silicon validation.\n\nExperience with gate‑level testing and multi‑clock design practices (CDC).\n\nBroad knowledge of chip design from micro‑architecture through physical design.\n\nKnowledge of design verification (DV) simulation methodologies.\n\nStrong programming and scripting skills in Perl, Python, or Tcl.\n\nExperience with industry standard DFT/SCAN/ATPG tools.\n\nExperience with STA constraints development and analysis for DFT modes.\n\nPractical experience with silicon debug.\n\nAmazon is an equal‑opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status.\n\n#J-18808-Ljbffr","datePosted":"2026-06-20T05:00:33.725Z","dateModified":"2026-06-20T05:00:33.725Z","hiringOrganization":{"@type":"Organization","name":"Amazon","sameAs":"https://jobsearcher.com"},"jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Austin","addressRegion":"TX","addressCountry":"US"}},"identifier":{"@type":"PropertyValue","name":"JobSearcher","value":"9643796cd6d5ba5f33b9614a"},"url":"https://jobsearcher.com/jobs/9643796cd6d5ba5f33b9614a"}}