{"schemaVersion":"jobsearcher.job.v1","id":"94dfb0907b4131efcbfa532a","url":"https://jobsearcher.com/jobs/94dfb0907b4131efcbfa532a","canonicalUrl":"https://jobsearcher.com/jobs/94dfb0907b4131efcbfa532a","title":"Packaging Tech Lead Design Engineer","description":"Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.\n\nAstera Labs is hiring a Tech Lead Design Engineer to help architect and deliver the connectivity silicon powering the world's largest AI clusters. You'll own design execution on complex blocks across our purpose-built products, working at the cutting edge of PCIe, CXL, Ethernet, and emerging rack-scale interconnect technologies.\n\nThis is a high-impact technical role at a hyper-growth company. You'll partner closely with architecture, verification, DFT, and physical design teams to take features from spec to silicon, while contributing to the design methodology that scales with our roadmap. If you want to ship silicon that defines AI infrastructure, this is the team.\n\nKey Responsibilities\n\nRTL Design & Implementation\n\nOwn RTL design for assigned blocks from microarchitecture through synthesis sign-off\n\nDevelop high-quality, synthesizable Verilog/SystemVerilog with strong attention to PPA\n\nDrive design reviews, lint, CDC, and timing closure activities to silicon-ready quality\n\nCross-Functional Execution\n\nPartner with architecture to translate specifications into implementation-ready microarchitecture\n\nCollaborate with verification on testplans, coverage closure, and bug triage\n\nWork with DFT and physical design teams on scan, BIST, floorplanning, and timing closure\n\nTechnical Leadership & Quality\n\nMentor junior engineers and contribute to design methodology, scripts, and best practices\n\nDebug complex pre-silicon and post-silicon issues across RTL, gate-level, and emulation environments\n\nDrive structured, data-driven design decisions in support of aggressive tapeout schedules\n\nBasic Qualifications\n\nBachelor's degree in Electrical Engineering, Computer Engineering, or related field\n\n5+ years of digital design experience, including at least one full chip from spec to tapeout\n\nStrong proficiency in Verilog/SystemVerilog, RTL coding, and synthesis flows\n\nHands-on experience with timing closure, CDC, lint, and low-power design techniques\n\nSolid understanding of high-speed serial interfaces (PCIe, Ethernet, or similar) and SoC integration\n\nPreferred Qualifications\n\nMS or PhD in Electrical Engineering or Computer Engineering\n\nExperience with PCIe Gen5/Gen6, CXL, UALink, UCIe, or Ethernet MAC/PCS designs\n\nFamiliarity with formal verification, emulation, or assertion-based methodologies\n\nBackground in advanced process nodes (7nm, 5nm, or below)\n\nStrong debug skills across pre-silicon and post-silicon environments\n\nSalary range is $185,000 to $240,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.\n\nWe know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\n\n#J-18808-Ljbffr","company":"Socket","rawCompany":"socket","city":"San Jose","state":"CA","isRemote":false,"isActive":false,"createdAt":"2026-09-02T03:33:52.894Z","occupations":[{"code":"17-2072.00","title":"Electronics Engineers, Except Computer","slug":"electronics-engineers-except-computer"},{"code":"17-2061.00","title":"Computer Hardware Engineers","slug":"computer-hardware-engineers"},{"code":"17-2199.00","title":"Engineers, All Other","slug":"engineers-all-other"}],"industries":[{"code":"334413","title":"Semiconductor and Related Device Manufacturing","slug":"semiconductor-and-related-device-manufacturing"},{"code":"541512","title":"Computer Systems Design Services","slug":"computer-systems-design-services"},{"code":"334111","title":"Electronic Computer Manufacturing","slug":"electronic-computer-manufacturing"}],"jobPosting":{"@context":"https://schema.org","@type":"JobPosting","title":"Packaging Tech Lead Design Engineer","description":"Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.\n\nAstera Labs is hiring a Tech Lead Design Engineer to help architect and deliver the connectivity silicon powering the world's largest AI clusters. You'll own design execution on complex blocks across our purpose-built products, working at the cutting edge of PCIe, CXL, Ethernet, and emerging rack-scale interconnect technologies.\n\nThis is a high-impact technical role at a hyper-growth company. You'll partner closely with architecture, verification, DFT, and physical design teams to take features from spec to silicon, while contributing to the design methodology that scales with our roadmap. If you want to ship silicon that defines AI infrastructure, this is the team.\n\nKey Responsibilities\n\nRTL Design & Implementation\n\nOwn RTL design for assigned blocks from microarchitecture through synthesis sign-off\n\nDevelop high-quality, synthesizable Verilog/SystemVerilog with strong attention to PPA\n\nDrive design reviews, lint, CDC, and timing closure activities to silicon-ready quality\n\nCross-Functional Execution\n\nPartner with architecture to translate specifications into implementation-ready microarchitecture\n\nCollaborate with verification on testplans, coverage closure, and bug triage\n\nWork with DFT and physical design teams on scan, BIST, floorplanning, and timing closure\n\nTechnical Leadership & Quality\n\nMentor junior engineers and contribute to design methodology, scripts, and best practices\n\nDebug complex pre-silicon and post-silicon issues across RTL, gate-level, and emulation environments\n\nDrive structured, data-driven design decisions in support of aggressive tapeout schedules\n\nBasic Qualifications\n\nBachelor's degree in Electrical Engineering, Computer Engineering, or related field\n\n5+ years of digital design experience, including at least one full chip from spec to tapeout\n\nStrong proficiency in Verilog/SystemVerilog, RTL coding, and synthesis flows\n\nHands-on experience with timing closure, CDC, lint, and low-power design techniques\n\nSolid understanding of high-speed serial interfaces (PCIe, Ethernet, or similar) and SoC integration\n\nPreferred Qualifications\n\nMS or PhD in Electrical Engineering or Computer Engineering\n\nExperience with PCIe Gen5/Gen6, CXL, UALink, UCIe, or Ethernet MAC/PCS designs\n\nFamiliarity with formal verification, emulation, or assertion-based methodologies\n\nBackground in advanced process nodes (7nm, 5nm, or below)\n\nStrong debug skills across pre-silicon and post-silicon environments\n\nSalary range is $185,000 to $240,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.\n\nWe know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\n\n#J-18808-Ljbffr","datePosted":"2026-09-02T03:33:52.894Z","dateModified":"2026-09-02T03:33:52.894Z","hiringOrganization":{"@type":"Organization","name":"Socket","sameAs":"https://jobsearcher.com"},"jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"San Jose","addressRegion":"CA","addressCountry":"US"}},"identifier":{"@type":"PropertyValue","name":"JobSearcher","value":"94dfb0907b4131efcbfa532a"},"url":"https://jobsearcher.com/jobs/94dfb0907b4131efcbfa532a"}}