{"schemaVersion":"jobsearcher.job.v1","id":"94a9cde81344d03ad343b4e4","url":"https://jobsearcher.com/jobs/94a9cde81344d03ad343b4e4","canonicalUrl":"https://jobsearcher.com/jobs/94a9cde81344d03ad343b4e4","title":"RTL Design Engineer","description":"Overview Please Note:\n1. If you are a first time user, please create your candidatelogin account before you apply for a job. (Click Sign In > Create Account)\n2. If you already have a Candidate Account, please Sign-In before you apply.\nJob Description Broadcom’s Central Engineering Group is seeking a candidate to lead the digital design and verification of a broad range of analog mixed signal IP and IOs, including leading-edge AI programs on advanced nodes. Joining a world-class team of engineers with a highly collaborative culture, the role offers opportunities for growth and development.\nDefine the digital architecture and verification strategies for complex AMS and IO subsytems\nDesign, synthesis, and verification of Verilog/SystemVerilog RTL.\nAnalysis, debug, and resolution of Lint and CDC issues in the design.\nDesign convergence to timing closure utilizing RTL optimization strategies.\nConduct formal verification of design with Synopsys Formality / Cadence Conformal.\nGenerate timing constraints for Synthesis and STA at the block-level and SoC top-level.\nDrive comprehensive test plans to ensure quality of design.\nCollaborate with cross-functional teams, ranging from analog/mixed-signal circuit designers to SoC-level system integration.\nCreate and maintain detailed specification, design, and verification documentation.\nResponsibilities Define the digital architecture and verification strategies for complex AMS and IO subsystems\nDesign, synthesis, and verification of Verilog/SystemVerilog RTL\nAnalyze, debug, and resolve Lint and CDC issues in the design\nDesign convergence to timing closure utilizing RTL optimization strategies\nConduct formal verification of design with Synopsys Formality / Cadence Conformal\nGenerate timing constraints for Synthesis and STA at the block-level and SoC top-level\nDrive comprehensive test plans to ensure quality of design\nCollaborate with cross-functional teams, ranging from analog/mixed-signal circuit designers to SoC-level system integration\nCreate and maintain detailed specification, design, and verification documentation\nQualifications MS +10 years of relevant industry experience.\nExperience with digital implementation flow from RTL synthesis to timing closure.\nDeep understanding of timing analysis with Primetime flow and generation of Liberty models.\nExperience with Tessent tool for DFT insertion and verification\nProficient with Perl, Python and Tcl scripting.\nStrong problem solving skills with attention to detail.\nMust be self-motivated and able to work effectively across internal and external engineering teams.\nHighly Desired Qualifications Solid understanding of transistor-level circuit behavior.\nFamiliar with Cadence Schematic/Layout, SPICE/Spectre circuit simulation.\nExperience with advanced FinFET process nodes , including features, technology limitations and PPA tradeoffs.\nAdditional Job Description Compensation and Benefits The annual base salary range for this position is$127,100- $203,400.\nThis position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.\nBroadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.\nBroadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.\nIf you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.\n\n#J-18808-Ljbffr","company":"Broadcom","rawCompany":"broadcom","city":"Irvine","state":"CA","isRemote":false,"isActive":true,"createdAt":"2026-06-20T04:15:46.114Z","occupations":[{"code":"17-2072.00","title":"Electronics Engineers, Except Computer","slug":"electronics-engineers-except-computer"},{"code":"17-2061.00","title":"Computer Hardware Engineers","slug":"computer-hardware-engineers"},{"code":"17-2199.00","title":"Engineers, All Other","slug":"engineers-all-other"}],"industries":[{"code":"334413","title":"Semiconductor and Related Device Manufacturing","slug":"semiconductor-and-related-device-manufacturing"},{"code":"334419","title":"Other Electronic Component Manufacturing","slug":"other-electronic-component-manufacturing"},{"code":"334418","title":"Printed Circuit Assembly (Electronic Assembly) Manufacturing","slug":"printed-circuit-assembly-electronic-assembly-manufacturing"}],"jobPosting":{"@context":"https://schema.org","@type":"JobPosting","title":"RTL Design Engineer","description":"Overview Please Note:\n1. If you are a first time user, please create your candidatelogin account before you apply for a job. (Click Sign In > Create Account)\n2. If you already have a Candidate Account, please Sign-In before you apply.\nJob Description Broadcom’s Central Engineering Group is seeking a candidate to lead the digital design and verification of a broad range of analog mixed signal IP and IOs, including leading-edge AI programs on advanced nodes. Joining a world-class team of engineers with a highly collaborative culture, the role offers opportunities for growth and development.\nDefine the digital architecture and verification strategies for complex AMS and IO subsytems\nDesign, synthesis, and verification of Verilog/SystemVerilog RTL.\nAnalysis, debug, and resolution of Lint and CDC issues in the design.\nDesign convergence to timing closure utilizing RTL optimization strategies.\nConduct formal verification of design with Synopsys Formality / Cadence Conformal.\nGenerate timing constraints for Synthesis and STA at the block-level and SoC top-level.\nDrive comprehensive test plans to ensure quality of design.\nCollaborate with cross-functional teams, ranging from analog/mixed-signal circuit designers to SoC-level system integration.\nCreate and maintain detailed specification, design, and verification documentation.\nResponsibilities Define the digital architecture and verification strategies for complex AMS and IO subsystems\nDesign, synthesis, and verification of Verilog/SystemVerilog RTL\nAnalyze, debug, and resolve Lint and CDC issues in the design\nDesign convergence to timing closure utilizing RTL optimization strategies\nConduct formal verification of design with Synopsys Formality / Cadence Conformal\nGenerate timing constraints for Synthesis and STA at the block-level and SoC top-level\nDrive comprehensive test plans to ensure quality of design\nCollaborate with cross-functional teams, ranging from analog/mixed-signal circuit designers to SoC-level system integration\nCreate and maintain detailed specification, design, and verification documentation\nQualifications MS +10 years of relevant industry experience.\nExperience with digital implementation flow from RTL synthesis to timing closure.\nDeep understanding of timing analysis with Primetime flow and generation of Liberty models.\nExperience with Tessent tool for DFT insertion and verification\nProficient with Perl, Python and Tcl scripting.\nStrong problem solving skills with attention to detail.\nMust be self-motivated and able to work effectively across internal and external engineering teams.\nHighly Desired Qualifications Solid understanding of transistor-level circuit behavior.\nFamiliar with Cadence Schematic/Layout, SPICE/Spectre circuit simulation.\nExperience with advanced FinFET process nodes , including features, technology limitations and PPA tradeoffs.\nAdditional Job Description Compensation and Benefits The annual base salary range for this position is$127,100- $203,400.\nThis position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.\nBroadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.\nBroadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.\nIf you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.\n\n#J-18808-Ljbffr","datePosted":"2026-06-20T04:15:46.114Z","dateModified":"2026-06-20T04:15:46.114Z","hiringOrganization":{"@type":"Organization","name":"Broadcom","sameAs":"https://jobsearcher.com"},"jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Irvine","addressRegion":"CA","addressCountry":"US"}},"identifier":{"@type":"PropertyValue","name":"JobSearcher","value":"94a9cde81344d03ad343b4e4"},"url":"https://jobsearcher.com/jobs/94a9cde81344d03ad343b4e4"}}