{"schemaVersion":"jobsearcher.job.v1","id":"8f618d6f72f8e10e71fca61d","url":"https://jobsearcher.com/jobs/8f618d6f72f8e10e71fca61d","canonicalUrl":"https://jobsearcher.com/jobs/8f618d6f72f8e10e71fca61d","title":"RTL Engineer","description":"About The RoleDesign the RTL that defines our AI accelerator. You'll architect and implement the digital blocks — compute datapath, memory subsystem, on-chip interconnect, and control logic — from microarchitecture spec through synthesis-ready, timing-clean RTL, and own those blocks end-to-end with architecture, DV, physical design, and DFT all the way to silicon.What You'll DoOwn RTL design of digital blocks/subsystems for our accelerator — microarchitecture definition, SystemVerilog implementation, and integrationTranslate architectural specs into efficient, synthesizable RTL that meets power/performance/area (PPA) targetsDrive microarchitecture trade-offs — pipelining, datapath vs. control, clock/power gating — for high-performance, low-power designPartner with DV on verification, PD on synthesis/timing/floorplan closure, and DFT on testabilityOwn block-level quality: synthesis, timing/constraints (SDC, STA), lint, and CDC signoffContribute to architecture definition and design reviews; debug across simulation, emulation, and post-silicon bring-upUse and develop AI-assisted tool flows to accelerate design and verificationWhat We're Looking ForStrong digital-design fundamentals and expert Verilog/SystemVerilog RTL5+ years designing complex digital blocks/SoCs taken to siliconSolid microarchitecture skills — pipelining, datapath/control, FIFOs, arbitration, memory subsystems, on-chip interconnect/NoCSynthesis & timing awareness — writing synthesizable RTL, SDC constraints, STA, clock/power gating, CDC, lintDemonstrated collaboration with DV, PD, and DFT across the full RTL2GDS flow to tapeoutScripting (Python/Tcl/) for design automation(Optional) AI/ML accelerator or high-performance compute-datapath design; low-power techniques (UPF); high-speed interfaces (HBM, PCIe, SerDes); advanced nodes (7nm or better); RISC-V/CPU design; FPGA prototypingCompensationFinal offers depend on level, location, and skills relevant to the role. Additional compensation: equity grant per company guidelines; medical / dental / vision; 401(k); standard PTO.Visa SponsorshipDensityAI sponsors qualified candidates for H-1B, O-1, TN, E-3, and other employment-based visas, and we welcome applicants on F-1 OPT and STEM-OPT. Work authorization is required at start; we provide immigration support to secure or transfer status.Export ControlsAspects of this role may involve access to information subject to U.S. export controls (EAR/ITAR). We may discuss licensing or scope adjustments during the interview.Equal OpportunityDensityAI is an Equal Opportunity Employer. We do not discriminate on the basis of race, color, religious creed, national origin, ancestry, physical or mental disability, medical condition, genetic information, marital status, sex, gender, gender identity, gender expression, age (40+), sexual orientation, military or veteran status, pregnancy, or any other status protected by law. We comply with the California CROWN Act and provide reasonable accommodations on request.Full compensation packages are based on candidate experience and relevant certifications.California pay range$250,000 - $375,000 USD","company":"Densityai","rawCompany":"densityai","city":"Mountain View","state":"HI","isRemote":false,"isActive":false,"createdAt":"2026-07-03T10:34:21.812Z","occupations":[{"code":"17-2061.00","title":"Computer Hardware Engineers","slug":"computer-hardware-engineers"},{"code":"17-2072.00","title":"Electronics Engineers, Except Computer","slug":"electronics-engineers-except-computer"},{"code":"15-1299.08","title":"Computer Systems Engineers/Architects","slug":"computer-systems-engineers-architects"}],"industries":[{"code":"334413","title":"Semiconductor and Related Device Manufacturing","slug":"semiconductor-and-related-device-manufacturing"},{"code":"541512","title":"Computer Systems Design Services","slug":"computer-systems-design-services"},{"code":"541715","title":"Research and Development in the Physical, Engineering, and Life Sciences (except Nanotechnology and Biotechnology)","slug":"research-and-development-in-the-physical-engineering-and-life-sciences-except-nanotechnology-and-biotechnology"}],"jobPosting":{"@context":"https://schema.org","@type":"JobPosting","title":"RTL Engineer","description":"About The RoleDesign the RTL that defines our AI accelerator. You'll architect and implement the digital blocks — compute datapath, memory subsystem, on-chip interconnect, and control logic — from microarchitecture spec through synthesis-ready, timing-clean RTL, and own those blocks end-to-end with architecture, DV, physical design, and DFT all the way to silicon.What You'll DoOwn RTL design of digital blocks/subsystems for our accelerator — microarchitecture definition, SystemVerilog implementation, and integrationTranslate architectural specs into efficient, synthesizable RTL that meets power/performance/area (PPA) targetsDrive microarchitecture trade-offs — pipelining, datapath vs. control, clock/power gating — for high-performance, low-power designPartner with DV on verification, PD on synthesis/timing/floorplan closure, and DFT on testabilityOwn block-level quality: synthesis, timing/constraints (SDC, STA), lint, and CDC signoffContribute to architecture definition and design reviews; debug across simulation, emulation, and post-silicon bring-upUse and develop AI-assisted tool flows to accelerate design and verificationWhat We're Looking ForStrong digital-design fundamentals and expert Verilog/SystemVerilog RTL5+ years designing complex digital blocks/SoCs taken to siliconSolid microarchitecture skills — pipelining, datapath/control, FIFOs, arbitration, memory subsystems, on-chip interconnect/NoCSynthesis & timing awareness — writing synthesizable RTL, SDC constraints, STA, clock/power gating, CDC, lintDemonstrated collaboration with DV, PD, and DFT across the full RTL2GDS flow to tapeoutScripting (Python/Tcl/) for design automation(Optional) AI/ML accelerator or high-performance compute-datapath design; low-power techniques (UPF); high-speed interfaces (HBM, PCIe, SerDes); advanced nodes (7nm or better); RISC-V/CPU design; FPGA prototypingCompensationFinal offers depend on level, location, and skills relevant to the role. Additional compensation: equity grant per company guidelines; medical / dental / vision; 401(k); standard PTO.Visa SponsorshipDensityAI sponsors qualified candidates for H-1B, O-1, TN, E-3, and other employment-based visas, and we welcome applicants on F-1 OPT and STEM-OPT. Work authorization is required at start; we provide immigration support to secure or transfer status.Export ControlsAspects of this role may involve access to information subject to U.S. export controls (EAR/ITAR). We may discuss licensing or scope adjustments during the interview.Equal OpportunityDensityAI is an Equal Opportunity Employer. We do not discriminate on the basis of race, color, religious creed, national origin, ancestry, physical or mental disability, medical condition, genetic information, marital status, sex, gender, gender identity, gender expression, age (40+), sexual orientation, military or veteran status, pregnancy, or any other status protected by law. We comply with the California CROWN Act and provide reasonable accommodations on request.Full compensation packages are based on candidate experience and relevant certifications.California pay range$250,000 - $375,000 USD","datePosted":"2026-07-03T10:34:21.812Z","dateModified":"2026-07-03T10:34:21.812Z","hiringOrganization":{"@type":"Organization","name":"Densityai","sameAs":"https://jobsearcher.com"},"jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Mountain View","addressRegion":"HI","addressCountry":"US"}},"identifier":{"@type":"PropertyValue","name":"JobSearcher","value":"8f618d6f72f8e10e71fca61d"},"url":"https://jobsearcher.com/jobs/8f618d6f72f8e10e71fca61d"}}