Interconnect Micro-architect/RTL Design Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHINGIs your CV ready If so, and you are confident this is the role for you, make sure to apply asap.At AMD, our mission is to build great products that accelerate next‐generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.Together, we advance your career.THE ROLEAMD is looking for an engineering leader passionate about driving the best Power, Performance, Area (PPA) of AMD's SoC coherent interconnects data fabrics IPs for next‐generation AMD AI devices. The ideal candidate will have proven experience in developing scalable, complex digital IP microarchitectures to deliver industry‐leading performance/area and performance/power. In this role the candidate will work with IP and SOC architecture teams, RTL design team, verification team, and physical design team to drive the RTL design and microarchitecture of modular network‐on‐chip IPs for AMD data‐center silicon SoCs. The candidate will drive new methodologies to build scalable, modular network‐on‐chips. You will be a member of a core team of incredibly talented industry specialists and will work with the latest and rapidly evolving hardware technologies for AMD data‐center SoCs.THE PERSONThe ideal candidate has passion for modern, complex microarchitecture and efficient digital design. Should have demonstrated experience in developing complex, highly scalable, modular microarchitectures for SOC with focus on coherent and non‐coherent switch‐fabric IP and must possess leadership and technical skills to influence and drive SOC methodologies to enable delivery of multiple highly complex, high‐quality SOCs in shorter time. Able to communicate effectively and work optimally with different teams across AMD.KEY RESPONSIBILITIESTechnical microarchitecture lead on AMD data fabric RTL design team focused on driving the best scalability, modularity, power, performance, and areaExplore and dive initiatives to achieve best switch fabric scalability, modularity, and reuse across multiple advanced data‐center AI accelerator SOCsDevelop technical relationship with broader AMD design community and peersStay informed on latest trends on innovations on switch‐fabric hardware architecture and implementationClose architecture and micro‐architecture requirements, drive technical specifications for data fabric IP to meet those requirements, and drive RTL executionWork cross‐functionally with IP/domain architects to identify and assess complex technical issues/risks and develop RTL and microarchitecture solutions to achieve requirementsKnowledge sharing and other contributions to AMD data fabric architecture and designWork closely with design teams for area and floorplan refinement, verification test‐plan reviews, timing targets, emulation plans, pre‐SI bug resolution and performance/power verification sign‐offsSupport post‐SI teams for product performance, power and functional issues debug/resolutionPREFERRED EXPERIENCEExperience with highly scalable, configurable switch fabrics (coherent and non‐coherent)Experience with modern heterogeneous systems including CPU, GPU, and AI acceleratorsExperience with SOC and IP creation automation for different microarchitecturesProven track record of defining and delivering complex IP and SOC microarchitecturesExpert level ability in optimizing and performing trade‐off analysis across multiple domains including PPA, design, microarchitecture, and architecture, verification, and scheduleExpertise in RTL design, Verilog and SystemVerilogDeep knowledge of front‐end toolsExperience with synthesis, static timing, DFTExposure to physical design and verification methodsExperience with scripting languages such as Perl, Python, Unix shells and Makefiles, and leveraging AI tools to improve productivityOutstanding foundation in systems & SoC architecture, with expertise in one or more of the following: CPU or GPU, memory sub‐systems, fabrics, CPU/GPU coherency, multimedia, I/O sub‐systems, clocks, resets, virtualization and securityExperience analyzing CPU, GPU or system‐level micro‐architectural features to identify performance bottlenecks within different workloadsDemonstrated expertise in power management microarchitecture, low‐power design and power optimization, along with power impact at architecture and logic designExcellent communication, management, and presentation skillsAdept at collaboration among top‐thinkers and senior architects and designers with strong interpersonal skills to work across teams in different geographiesACADEMIC CREDENTIALSBachelors or masters degree in computer engineering / electrical engineering preferredLOCATIONSanta Clara, CABENEFITSAMD benefits at a glance.EEO STATEMENTAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee‐based recruitment services. xmcpwfu AMD and its subsidiaries are equal‐opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‐party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.