{"schemaVersion":"jobsearcher.job.v1","id":"8a756269af29a7dcb97809a9","url":"https://jobsearcher.com/jobs/8a756269af29a7dcb97809a9","canonicalUrl":"https://jobsearcher.com/jobs/8a756269af29a7dcb97809a9","title":"Physical Design Engineer, FullChip/ASIC Implementation","description":"In most instances, this position requires in-person interviews as part of the hiring process.\nMinimum qualifications:\nBachelor's degree in Electrical Engineering or equivalent practical experience.\n4 years of experience in physical design.\nExperience in one or more synthesis/PnR tools (e.g., Genus, Innovus, DC, ICC).\nExperience in high-performance synthesis, PnR, sign-off convergence, including STA and sign-off optimizations.\n\nPreferred qualifications:\nExperience in top-level floorplanning and block integration.\nExperience in low power design implementation including UPF/CPF, multi-voltage domains and power gating.\nExperience with ASIC design flows and methodology of physical design.\nUnderstanding of circuit design, device physics, and deep submicron technology.\nKnowledge of Verilog/SystemVerilog and fundamentals of computer architecture.\nEffective skills with scripting languages such as Tcl, or Perl.\nAbout the job\n\nBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.\n\nGoogle's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.\n\nIndividual pay is determined by factors including job-related skills, experience, and relevant education or training.\n\nUS: $138000 - $197000 (USD) + 15% bonus target + equity + benefits\n\nLearn more about benefits at Google.\nResponsibilities\nDevelop all aspects of ASIC RTL2GDS implementation for high Performance, Power, Area (PPA) designs.\nManage full-chip level physical implementation.\nDefine and implement innovative schemes to improve performance and power.\nWork with cross-functional teams to deliver best quality of results.\nGoogle is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.","company":"Google","rawCompany":"google","city":"Mountain View","state":"HI","isRemote":false,"isActive":false,"createdAt":"2026-09-06T08:22:14.728Z","occupations":[{"code":"17-2061.00","title":"Computer Hardware Engineers","slug":"computer-hardware-engineers"},{"code":"17-2072.00","title":"Electronics Engineers, Except Computer","slug":"electronics-engineers-except-computer"},{"code":"17-2199.00","title":"Engineers, All Other","slug":"engineers-all-other"}],"industries":[{"code":"334413","title":"Semiconductor and Related Device Manufacturing","slug":"semiconductor-and-related-device-manufacturing"},{"code":"334419","title":"Other Electronic Component Manufacturing","slug":"other-electronic-component-manufacturing"},{"code":"334111","title":"Electronic Computer Manufacturing","slug":"electronic-computer-manufacturing"}],"jobPosting":{"@context":"https://schema.org","@type":"JobPosting","title":"Physical Design Engineer, FullChip/ASIC Implementation","description":"In most instances, this position requires in-person interviews as part of the hiring process.\nMinimum qualifications:\nBachelor's degree in Electrical Engineering or equivalent practical experience.\n4 years of experience in physical design.\nExperience in one or more synthesis/PnR tools (e.g., Genus, Innovus, DC, ICC).\nExperience in high-performance synthesis, PnR, sign-off convergence, including STA and sign-off optimizations.\n\nPreferred qualifications:\nExperience in top-level floorplanning and block integration.\nExperience in low power design implementation including UPF/CPF, multi-voltage domains and power gating.\nExperience with ASIC design flows and methodology of physical design.\nUnderstanding of circuit design, device physics, and deep submicron technology.\nKnowledge of Verilog/SystemVerilog and fundamentals of computer architecture.\nEffective skills with scripting languages such as Tcl, or Perl.\nAbout the job\n\nBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.\n\nGoogle's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.\n\nIndividual pay is determined by factors including job-related skills, experience, and relevant education or training.\n\nUS: $138000 - $197000 (USD) + 15% bonus target + equity + benefits\n\nLearn more about benefits at Google.\nResponsibilities\nDevelop all aspects of ASIC RTL2GDS implementation for high Performance, Power, Area (PPA) designs.\nManage full-chip level physical implementation.\nDefine and implement innovative schemes to improve performance and power.\nWork with cross-functional teams to deliver best quality of results.\nGoogle is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.","datePosted":"2026-09-06T08:22:14.728Z","dateModified":"2026-09-06T08:22:14.728Z","hiringOrganization":{"@type":"Organization","name":"Google","sameAs":"https://jobsearcher.com"},"jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Mountain View","addressRegion":"HI","addressCountry":"US"}},"identifier":{"@type":"PropertyValue","name":"JobSearcher","value":"8a756269af29a7dcb97809a9"},"url":"https://jobsearcher.com/jobs/8a756269af29a7dcb97809a9"}}