{"schemaVersion":"jobsearcher.job.v1","id":"7a52dd65193c65cc63de7f4e","url":"https://jobsearcher.com/jobs/7a52dd65193c65cc63de7f4e","canonicalUrl":"https://jobsearcher.com/jobs/7a52dd65193c65cc63de7f4e","title":"Senior Silicon Development Engineer DFT & Bring-Up","description":"AMD in San Jose, CA is seeking a DFT engineer to implement and verify DFT architectures and features. You will perform scan insertion, ATPG pattern generation, and gate-level ATPG verification, contributing to post-silicon yield learning.\nThe candidate should have hands-on experience with DFT methodologies, Mentor Testkompress or Synopsys Tetramax/DFTMAX, and Verilog RTL design, with strong problem-solving and communication skills.\n\n#J-18808-Ljbffr","company":"Socket","rawCompany":"socket","city":"San Jose","state":"CA","isRemote":false,"isActive":false,"createdAt":"2026-09-09T03:47:33.573Z","occupations":[{"code":"17-2061.00","title":"Computer Hardware Engineers","slug":"computer-hardware-engineers"},{"code":"17-2072.00","title":"Electronics Engineers, Except Computer","slug":"electronics-engineers-except-computer"},{"code":"15-1299.08","title":"Computer Systems Engineers/Architects","slug":"computer-systems-engineers-architects"}],"industries":[{"code":"334413","title":"Semiconductor and Related Device Manufacturing","slug":"semiconductor-and-related-device-manufacturing"},{"code":"334111","title":"Electronic Computer Manufacturing","slug":"electronic-computer-manufacturing"},{"code":"333242","title":"Semiconductor Machinery Manufacturing","slug":"semiconductor-machinery-manufacturing"}],"jobPosting":{"@context":"https://schema.org","@type":"JobPosting","title":"Senior Silicon Development Engineer DFT & Bring-Up","description":"AMD in San Jose, CA is seeking a DFT engineer to implement and verify DFT architectures and features. You will perform scan insertion, ATPG pattern generation, and gate-level ATPG verification, contributing to post-silicon yield learning.\nThe candidate should have hands-on experience with DFT methodologies, Mentor Testkompress or Synopsys Tetramax/DFTMAX, and Verilog RTL design, with strong problem-solving and communication skills.\n\n#J-18808-Ljbffr","datePosted":"2026-09-09T03:47:33.573Z","dateModified":"2026-09-09T03:47:33.573Z","hiringOrganization":{"@type":"Organization","name":"Socket","sameAs":"https://jobsearcher.com"},"jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"San Jose","addressRegion":"CA","addressCountry":"US"}},"identifier":{"@type":"PropertyValue","name":"JobSearcher","value":"7a52dd65193c65cc63de7f4e"},"url":"https://jobsearcher.com/jobs/7a52dd65193c65cc63de7f4e"}}