{"schemaVersion":"jobsearcher.job.v1","id":"78eea5b2e830fe628dc7353c","url":"https://jobsearcher.com/jobs/78eea5b2e830fe628dc7353c","canonicalUrl":"https://jobsearcher.com/jobs/78eea5b2e830fe628dc7353c","title":"Sr Design Verification Engineer - RISC-V & CPU","description":"Design Verification Engineer - Senior Level (15+ years)Duration: 10-12+ Months ContractLocations: Remote (California, oregon, Washington)Pay Range: $80-$85/hr on W2, 40 HrsDescription:The top 6 are must skills and rest are preferred skills, and of course it goes without saying that basic DV skills such as System Verilog/UVM, assertions, coverage, random constraints, etc.1)RISC-V architecture knowledge and verification experience2)VC Formal DPV App (Datapath Verification) which checks the RTL against C/C++ models for arithmetic conformance3)L3 cache coherent system with AXI and CHI interfaces4)C/C++5)Synopsys tools, VCS, VC Formal6)Python based simulation flow7)Wide Vector Unit and a Matmul Unit.8)Formal verification9)SOC System integration is also required, like booting Linux OS10)GLS (Gate Level Simulation)11)Low Power experience (CPF/UPF)","company":"Experis","rawCompany":"experis","city":"Mountain View","state":"CA","isRemote":false,"isActive":false,"createdAt":"2026-05-02T12:10:48.795Z","occupations":[{"code":"17-2061.00","title":"Computer Hardware Engineers","slug":"computer-hardware-engineers"},{"code":"17-2112.02","title":"Validation Engineers","slug":"validation-engineers"},{"code":"15-1299.08","title":"Computer Systems Engineers/Architects","slug":"computer-systems-engineers-architects"}],"industries":[{"code":"541512","title":"Computer Systems Design Services","slug":"computer-systems-design-services"},{"code":"541330","title":"Engineering Services","slug":"engineering-services"},{"code":"541715","title":"Research and Development in the Physical, Engineering, and Life Sciences (except Nanotechnology and Biotechnology)","slug":"research-and-development-in-the-physical-engineering-and-life-sciences-except-nanotechnology-and-biotechnology"}],"jobPosting":{"@context":"https://schema.org","@type":"JobPosting","title":"Sr Design Verification Engineer - RISC-V & CPU","description":"Design Verification Engineer - Senior Level (15+ years)Duration: 10-12+ Months ContractLocations: Remote (California, oregon, Washington)Pay Range: $80-$85/hr on W2, 40 HrsDescription:The top 6 are must skills and rest are preferred skills, and of course it goes without saying that basic DV skills such as System Verilog/UVM, assertions, coverage, random constraints, etc.1)RISC-V architecture knowledge and verification experience2)VC Formal DPV App (Datapath Verification) which checks the RTL against C/C++ models for arithmetic conformance3)L3 cache coherent system with AXI and CHI interfaces4)C/C++5)Synopsys tools, VCS, VC Formal6)Python based simulation flow7)Wide Vector Unit and a Matmul Unit.8)Formal verification9)SOC System integration is also required, like booting Linux OS10)GLS (Gate Level Simulation)11)Low Power experience (CPF/UPF)","datePosted":"2026-05-02T12:10:48.795Z","dateModified":"2026-05-02T12:10:48.795Z","hiringOrganization":{"@type":"Organization","name":"Experis","sameAs":"https://jobsearcher.com"},"jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Mountain View","addressRegion":"CA","addressCountry":"US"}},"identifier":{"@type":"PropertyValue","name":"JobSearcher","value":"78eea5b2e830fe628dc7353c"},"url":"https://jobsearcher.com/jobs/78eea5b2e830fe628dc7353c"}}