{"schemaVersion":"jobsearcher.job.v1","id":"77fb2dd4f8d472f7dcd324f6","url":"https://jobsearcher.com/jobs/77fb2dd4f8d472f7dcd324f6","canonicalUrl":"https://jobsearcher.com/jobs/77fb2dd4f8d472f7dcd324f6","title":"DFT Engineer (Scan / MBIST / ATPG)","description":"Job Description:Position: DFT Engineer (Scan / MBIST / ATPG)Location: Mountain View CA (On-site)Hire Type: Full Time / ContractWe are seeking a DFT Engineer with hands-on experience in Scan, MBIST, ATPG generation, and pattern simulation for complex SoC/IP designs.Key Responsibilities:• Develop and implement Design-for-Test (DFT) architecture for IPs and SoCs.• Perform Scan insertion and Scan chain verification.• Integrate and validate MBIST solutions for embedded memories.• Generate ATPG patterns for stuck-at, transition, and other manufacturing fault models.• Execute ATPG simulation and pattern verification to ensure coverage and pattern quality.• Analyze and improve fault coverage while reducing pattern count.• Debug DFT-related issues during implementation and verification.• Collaborate with RTL, Physical Design, Verification, and Test Engineering teams.• Support silicon bring-up and production test activities when required.Required Skills:• Strong understanding of DFT fundamentals.• Hands-on experience in:o Scan Architectureo Scan Insertiono Scan Compressiono MBIST Integrationo ATPG Pattern Generationo ATPG Simulationo Fault Coverage Analysiso DFT Verification• Experience with industry-standard DFT tools such as:o Tessento Synopsys DFT Compilero TetraMAX / TestMAX ATPGo Modus (preferred)• Good knowledge of Verilog/SystemVerilog and simulation environments.• Familiarity with manufacturing test concepts and silicon debug.Preferred Qualifications:• Experience with large SoC or CPU/GPU designs.• Knowledge of IJTAG, Boundary Scan (JTAG), LBIST, and Test Compression.• Experience supporting post-silicon test and yield improvement activities","company":"Programmers.io","rawCompany":"programmersio","city":"Mountain View","state":"CA","isRemote":false,"isActive":true,"createdAt":"2026-06-29T23:50:51.516Z","occupations":[{"code":"17-2072.00","title":"Electronics Engineers, Except Computer","slug":"electronics-engineers-except-computer"},{"code":"15-1299.08","title":"Computer Systems Engineers/Architects","slug":"computer-systems-engineers-architects"},{"code":"17-2061.00","title":"Computer Hardware Engineers","slug":"computer-hardware-engineers"}],"industries":[{"code":"334413","title":"Semiconductor and Related Device Manufacturing","slug":"semiconductor-and-related-device-manufacturing"},{"code":"541512","title":"Computer Systems Design Services","slug":"computer-systems-design-services"},{"code":"334111","title":"Electronic Computer Manufacturing","slug":"electronic-computer-manufacturing"}],"jobPosting":{"@context":"https://schema.org","@type":"JobPosting","title":"DFT Engineer (Scan / MBIST / ATPG)","description":"Job Description:Position: DFT Engineer (Scan / MBIST / ATPG)Location: Mountain View CA (On-site)Hire Type: Full Time / ContractWe are seeking a DFT Engineer with hands-on experience in Scan, MBIST, ATPG generation, and pattern simulation for complex SoC/IP designs.Key Responsibilities:• Develop and implement Design-for-Test (DFT) architecture for IPs and SoCs.• Perform Scan insertion and Scan chain verification.• Integrate and validate MBIST solutions for embedded memories.• Generate ATPG patterns for stuck-at, transition, and other manufacturing fault models.• Execute ATPG simulation and pattern verification to ensure coverage and pattern quality.• Analyze and improve fault coverage while reducing pattern count.• Debug DFT-related issues during implementation and verification.• Collaborate with RTL, Physical Design, Verification, and Test Engineering teams.• Support silicon bring-up and production test activities when required.Required Skills:• Strong understanding of DFT fundamentals.• Hands-on experience in:o Scan Architectureo Scan Insertiono Scan Compressiono MBIST Integrationo ATPG Pattern Generationo ATPG Simulationo Fault Coverage Analysiso DFT Verification• Experience with industry-standard DFT tools such as:o Tessento Synopsys DFT Compilero TetraMAX / TestMAX ATPGo Modus (preferred)• Good knowledge of Verilog/SystemVerilog and simulation environments.• Familiarity with manufacturing test concepts and silicon debug.Preferred Qualifications:• Experience with large SoC or CPU/GPU designs.• Knowledge of IJTAG, Boundary Scan (JTAG), LBIST, and Test Compression.• Experience supporting post-silicon test and yield improvement activities","datePosted":"2026-06-29T23:50:51.516Z","dateModified":"2026-06-29T23:50:51.516Z","hiringOrganization":{"@type":"Organization","name":"Programmers.io","sameAs":"https://jobsearcher.com"},"jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Mountain View","addressRegion":"CA","addressCountry":"US"}},"identifier":{"@type":"PropertyValue","name":"JobSearcher","value":"77fb2dd4f8d472f7dcd324f6"},"url":"https://jobsearcher.com/jobs/77fb2dd4f8d472f7dcd324f6"}}