{"schemaVersion":"jobsearcher.job.v1","id":"75ea2d22deff5f34d5b33665","url":"https://jobsearcher.com/jobs/75ea2d22deff5f34d5b33665","canonicalUrl":"https://jobsearcher.com/jobs/75ea2d22deff5f34d5b33665","title":"System Architect","description":"Austin, Texas, USA\nOR\nPortland, Oregon, USA\nOR\n\nResponsibilities\nDefine and document system-level architecture, data flows, memory maps, and transaction models for high-performance computing systems; specify NoC topology, power domains, clock domains, and interface requirements.\nDefine how the product is partitioned across dies, the die-to-die topology, and how memory is provisioned across the package.\nBuild and extend system-level performance models to evaluate partitioning options, die-to-die topology, memory provisioning and package composition.\nRun workload-driven analysis to set credible targets and test whether architectural choices meet them.\nQuantify what crosses the die boundary for a given partitioning, and what that costs in bandwidth, latency and power.\nCorrelate architectural models against detailed microarchitectural models, and both against RTL, so projections can be trusted.\nOwn the correlation methodology and the regression infrastructure that keeps it honest as the design moves.\nDiagnose divergence between model and implementation and drive it to root cause.\nTurn model output into architectural recommendations, with the assumptions and sensitivities stated.\nCoordinate delivery and integration of internal and external IP, including interconnects such as PCIe, DDR, HBM, and AMBA CHI NoC.\nWork with foundry and design service partners on SOW definition and technical deliverable management.\nDefine and drive PPA targets at chip, subsystem, and IP levels.\nCollaborate with firmware, software, and verification teams on functional and PPA requirements.\nRepresent architecture decisions across teams, and mentor other engineers as the role grows.\nQualifications & Skills\nBachelor's, Master's or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.\n6+ years in SoC or ASIC architecture, design or integration, or in system-level performance modelling.\nStrong knowledge of SoC architecture and design principles.\nExperience documenting system-level architecture requirements.\nExperience with on-chip interconnect protocols and architectures.\nDemonstrated experience building or substantially extending performance models used to make real design decisions.\nProficiency in C++ and Python for modelling, analysis and automation.\nAbility to present a quantitative argument clearly enough to change an architectural decision.\nStrong written and verbal communication, and the ability to lead vendor discussions.\nPreferred Qualifications & Skills\nRISC-V or Arm CPU architecture, including cache and memory hierarchy design.\nAMBA CHI network-on-chip, and system-level cache behaviour.\nAdvanced packaging: 2.5D and 3D integration, chiplet architectures, and die-to-die interfaces such as UCIe, BoW and CoWoS, including partitioning and floorplan trade-offs.\nExperience correlating a performance model against RTL on a program that reached silicon.\nLPDDR or HBM memory subsystem modelling — scheduling, page policy, bank and rank parallelism.\nWorkload characterisation methodology, including reuse-distance and roofline analysis.\nFoundry ecosystem familiarity, including scaling behaviour across node transitions.\nPCIe, UCIe, DDR/LPDDR and HBM.\nHigh-performance or server-class CPU experience.\nWhat We Offer\nLead impactful architecture decisions shaping next-generation heterogeneous computing\nCompetitive compensation & benefits package\nCollaboration with talented engineers passionate about cutting-edge CPU technologies.\nOpportunities for professional growth in an innovative, fast-paced environment\nA flexible and inclusive work culture","company":"Aheadcomputing","rawCompany":"aheadcomputing","city":"Gladstone","state":"OR","isRemote":false,"isActive":false,"createdAt":"2026-10-30T09:37:41.174Z","occupations":[{"code":"15-1299.08","title":"Computer Systems Engineers/Architects","slug":"computer-systems-engineers-architects"},{"code":"17-2061.00","title":"Computer Hardware Engineers","slug":"computer-hardware-engineers"},{"code":"17-2199.00","title":"Engineers, All Other","slug":"engineers-all-other"}],"industries":[{"code":"541512","title":"Computer Systems Design Services","slug":"computer-systems-design-services"},{"code":"334111","title":"Electronic Computer Manufacturing","slug":"electronic-computer-manufacturing"},{"code":"513210","title":"Software Publishers","slug":"software-publishers"}],"jobPosting":{"@context":"https://schema.org","@type":"JobPosting","title":"System Architect","description":"Austin, Texas, USA\nOR\nPortland, Oregon, USA\nOR\n\nResponsibilities\nDefine and document system-level architecture, data flows, memory maps, and transaction models for high-performance computing systems; specify NoC topology, power domains, clock domains, and interface requirements.\nDefine how the product is partitioned across dies, the die-to-die topology, and how memory is provisioned across the package.\nBuild and extend system-level performance models to evaluate partitioning options, die-to-die topology, memory provisioning and package composition.\nRun workload-driven analysis to set credible targets and test whether architectural choices meet them.\nQuantify what crosses the die boundary for a given partitioning, and what that costs in bandwidth, latency and power.\nCorrelate architectural models against detailed microarchitectural models, and both against RTL, so projections can be trusted.\nOwn the correlation methodology and the regression infrastructure that keeps it honest as the design moves.\nDiagnose divergence between model and implementation and drive it to root cause.\nTurn model output into architectural recommendations, with the assumptions and sensitivities stated.\nCoordinate delivery and integration of internal and external IP, including interconnects such as PCIe, DDR, HBM, and AMBA CHI NoC.\nWork with foundry and design service partners on SOW definition and technical deliverable management.\nDefine and drive PPA targets at chip, subsystem, and IP levels.\nCollaborate with firmware, software, and verification teams on functional and PPA requirements.\nRepresent architecture decisions across teams, and mentor other engineers as the role grows.\nQualifications & Skills\nBachelor's, Master's or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.\n6+ years in SoC or ASIC architecture, design or integration, or in system-level performance modelling.\nStrong knowledge of SoC architecture and design principles.\nExperience documenting system-level architecture requirements.\nExperience with on-chip interconnect protocols and architectures.\nDemonstrated experience building or substantially extending performance models used to make real design decisions.\nProficiency in C++ and Python for modelling, analysis and automation.\nAbility to present a quantitative argument clearly enough to change an architectural decision.\nStrong written and verbal communication, and the ability to lead vendor discussions.\nPreferred Qualifications & Skills\nRISC-V or Arm CPU architecture, including cache and memory hierarchy design.\nAMBA CHI network-on-chip, and system-level cache behaviour.\nAdvanced packaging: 2.5D and 3D integration, chiplet architectures, and die-to-die interfaces such as UCIe, BoW and CoWoS, including partitioning and floorplan trade-offs.\nExperience correlating a performance model against RTL on a program that reached silicon.\nLPDDR or HBM memory subsystem modelling — scheduling, page policy, bank and rank parallelism.\nWorkload characterisation methodology, including reuse-distance and roofline analysis.\nFoundry ecosystem familiarity, including scaling behaviour across node transitions.\nPCIe, UCIe, DDR/LPDDR and HBM.\nHigh-performance or server-class CPU experience.\nWhat We Offer\nLead impactful architecture decisions shaping next-generation heterogeneous computing\nCompetitive compensation & benefits package\nCollaboration with talented engineers passionate about cutting-edge CPU technologies.\nOpportunities for professional growth in an innovative, fast-paced environment\nA flexible and inclusive work culture","datePosted":"2026-10-30T09:37:41.174Z","dateModified":"2026-10-30T09:37:41.174Z","hiringOrganization":{"@type":"Organization","name":"Aheadcomputing","sameAs":"https://jobsearcher.com"},"jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Gladstone","addressRegion":"OR","addressCountry":"US"}},"identifier":{"@type":"PropertyValue","name":"JobSearcher","value":"75ea2d22deff5f34d5b33665"},"url":"https://jobsearcher.com/jobs/75ea2d22deff5f34d5b33665"}}