{"schemaVersion":"jobsearcher.job.v1","id":"75c4683c81b6d36046861efd","url":"https://jobsearcher.com/jobs/75c4683c81b6d36046861efd","canonicalUrl":"https://jobsearcher.com/jobs/75c4683c81b6d36046861efd","title":"Senior Technical Architect - C, Post - silicon Validation, Python","description":"Job Summary\n\nRequirements:\n10+ years post-silicon electrical characterization, HSIO validation, or memory electrical validation of SoC PHYs\nHands-on ownership of PCIe or Ethernet and some experience with UFS or LPDDR5.\nLab fluency: high-speed oscilloscopes, BERT, VNA/TDR, protocol and logic analyzers; you have personally taken eyes, jitter, BER, and S-parameter data and used it to close a silicon issue\nWorking knowledge of signal integrity, SerDes, silicon PVT sensitivity, and JEDEC / PCI-SIG / MIPI-UFS electrical specs\nAbility to read schematics and layout, debug at the probe point, and separate PHY vs. package vs. board vs. firmware\nScripting for lab automation and data analysis (Python preferred)\nClear written and verbal communication;\n\nPresent a margin plot and a root-cause story to design and program teams\n\nKey Responsibilities\n\nRequirements:\n10+ years post-silicon electrical characterization, HSIO validation, or memory electrical validation of SoC PHYs\nHands-on ownership of PCIe or Ethernet and some experience with UFS or LPDDR5.\nLab fluency: high-speed oscilloscopes, BERT, VNA/TDR, protocol and logic analyzers; you have personally taken eyes, jitter, BER, and S-parameter data and used it to close a silicon issue\nWorking knowledge of signal integrity, SerDes, silicon PVT sensitivity, and JEDEC / PCI-SIG / MIPI-UFS electrical specs\nAbility to read schematics and layout, debug at the probe point, and separate PHY vs. package vs. board vs. firmware\nScripting for lab automation and data analysis (Python preferred)\nClear written and verbal communication\n\nPresent a margin plot and a root-cause story to design and program teams\n\nSkill Requirements\n\nRequirements:\n10+ years post-silicon electrical characterization, HSIO validation, or memory electrical validation of SoC PHYs\nHands-on ownership of PCIe or Ethernet and some experience with UFS or LPDDR5.\nLab fluency: high-speed oscilloscopes, BERT, VNA/TDR, protocol and logic analyzers; you have personally taken eyes, jitter, BER, and S-parameter data and used it to close a silicon issue\nWorking knowledge of signal integrity, SerDes, silicon PVT sensitivity, and JEDEC / PCI-SIG / MIPI-UFS electrical specs\nAbility to read schematics and layout, debug at the probe point, and separate PHY vs. package vs. board vs. firmware\nScripting for lab automation and data analysis (Python preferred)\nClear written and verbal communication\n\nPresent a margin plot and a root-cause story to design and program teams\n\nMust Have Skill\nC,Post Silicon Validation,Python\nGood to Have Skill\nOther Requirements\n\nRequirements:\n10+ years post-silicon electrical characterization, HSIO validation, or memory electrical validation of SoC PHYs\nHands-on ownership of PCIe or Ethernet and some experience with UFS or LPDDR5.\nLab fluency: high-speed oscilloscopes, BERT, VNA/TDR, protocol and logic analyzers; you have personally taken eyes, jitter, BER, and S-parameter data and used it to close a silicon issue\nWorking knowledge of signal integrity, SerDes, silicon PVT sensitivity, and JEDEC / PCI-SIG / MIPI-UFS electrical specs\nAbility to read schematics and layout, debug at the probe point, and separate PHY vs. package vs. board vs. firmware\nScripting for lab automation and data analysis (Python preferred)\nClear written and verbal communication\n\nPresent a margin plot and a root-cause story to design and program teams","company":"HCLTech","rawCompany":"hcltech","city":"Denver","state":"CO","isRemote":false,"isActive":false,"createdAt":"2026-10-16T11:33:16.660Z","occupations":[{"code":"17-2061.00","title":"Computer Hardware Engineers","slug":"computer-hardware-engineers"},{"code":"17-2072.00","title":"Electronics Engineers, Except Computer","slug":"electronics-engineers-except-computer"},{"code":"15-1299.08","title":"Computer Systems Engineers/Architects","slug":"computer-systems-engineers-architects"}],"industries":[{"code":"334413","title":"Semiconductor and Related Device Manufacturing","slug":"semiconductor-and-related-device-manufacturing"},{"code":"334111","title":"Electronic Computer Manufacturing","slug":"electronic-computer-manufacturing"},{"code":"541512","title":"Computer Systems Design Services","slug":"computer-systems-design-services"}],"jobPosting":{"@context":"https://schema.org","@type":"JobPosting","title":"Senior Technical Architect - C, Post - silicon Validation, Python","description":"Job Summary\n\nRequirements:\n10+ years post-silicon electrical characterization, HSIO validation, or memory electrical validation of SoC PHYs\nHands-on ownership of PCIe or Ethernet and some experience with UFS or LPDDR5.\nLab fluency: high-speed oscilloscopes, BERT, VNA/TDR, protocol and logic analyzers; you have personally taken eyes, jitter, BER, and S-parameter data and used it to close a silicon issue\nWorking knowledge of signal integrity, SerDes, silicon PVT sensitivity, and JEDEC / PCI-SIG / MIPI-UFS electrical specs\nAbility to read schematics and layout, debug at the probe point, and separate PHY vs. package vs. board vs. firmware\nScripting for lab automation and data analysis (Python preferred)\nClear written and verbal communication;\n\nPresent a margin plot and a root-cause story to design and program teams\n\nKey Responsibilities\n\nRequirements:\n10+ years post-silicon electrical characterization, HSIO validation, or memory electrical validation of SoC PHYs\nHands-on ownership of PCIe or Ethernet and some experience with UFS or LPDDR5.\nLab fluency: high-speed oscilloscopes, BERT, VNA/TDR, protocol and logic analyzers; you have personally taken eyes, jitter, BER, and S-parameter data and used it to close a silicon issue\nWorking knowledge of signal integrity, SerDes, silicon PVT sensitivity, and JEDEC / PCI-SIG / MIPI-UFS electrical specs\nAbility to read schematics and layout, debug at the probe point, and separate PHY vs. package vs. board vs. firmware\nScripting for lab automation and data analysis (Python preferred)\nClear written and verbal communication\n\nPresent a margin plot and a root-cause story to design and program teams\n\nSkill Requirements\n\nRequirements:\n10+ years post-silicon electrical characterization, HSIO validation, or memory electrical validation of SoC PHYs\nHands-on ownership of PCIe or Ethernet and some experience with UFS or LPDDR5.\nLab fluency: high-speed oscilloscopes, BERT, VNA/TDR, protocol and logic analyzers; you have personally taken eyes, jitter, BER, and S-parameter data and used it to close a silicon issue\nWorking knowledge of signal integrity, SerDes, silicon PVT sensitivity, and JEDEC / PCI-SIG / MIPI-UFS electrical specs\nAbility to read schematics and layout, debug at the probe point, and separate PHY vs. package vs. board vs. firmware\nScripting for lab automation and data analysis (Python preferred)\nClear written and verbal communication\n\nPresent a margin plot and a root-cause story to design and program teams\n\nMust Have Skill\nC,Post Silicon Validation,Python\nGood to Have Skill\nOther Requirements\n\nRequirements:\n10+ years post-silicon electrical characterization, HSIO validation, or memory electrical validation of SoC PHYs\nHands-on ownership of PCIe or Ethernet and some experience with UFS or LPDDR5.\nLab fluency: high-speed oscilloscopes, BERT, VNA/TDR, protocol and logic analyzers; you have personally taken eyes, jitter, BER, and S-parameter data and used it to close a silicon issue\nWorking knowledge of signal integrity, SerDes, silicon PVT sensitivity, and JEDEC / PCI-SIG / MIPI-UFS electrical specs\nAbility to read schematics and layout, debug at the probe point, and separate PHY vs. package vs. board vs. firmware\nScripting for lab automation and data analysis (Python preferred)\nClear written and verbal communication\n\nPresent a margin plot and a root-cause story to design and program teams","datePosted":"2026-10-16T11:33:16.660Z","dateModified":"2026-10-16T11:33:16.660Z","hiringOrganization":{"@type":"Organization","name":"HCLTech","sameAs":"https://jobsearcher.com"},"jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Denver","addressRegion":"CO","addressCountry":"US"}},"identifier":{"@type":"PropertyValue","name":"JobSearcher","value":"75c4683c81b6d36046861efd"},"url":"https://jobsearcher.com/jobs/75c4683c81b6d36046861efd"}}