{"schemaVersion":"jobsearcher.job.v1","id":"74954d2e40f4fc3dadc13ea7","url":"https://jobsearcher.com/jobs/74954d2e40f4fc3dadc13ea7","canonicalUrl":"https://jobsearcher.com/jobs/74954d2e40f4fc3dadc13ea7","title":"Machine Learning Systems Intern","description":"Hybrid SSM‑Transformer models have a unique advantage for on‑chip memory efficiency:SSM layerscompress sequence history into a fixed‑size recurrent state\r\nAttention layersstore key‑value caches that grow with context lengthThis leads to an important design question:\r\nFor a given model configuration and maximum context length, can on‑chip SRAM be sized so that inference runs entirely on chip—eliminating the need for slower off‑chip HBM or DRAM?What the intern will work on:The intern will model and analyze memory behavior during inference of hybrid SSM‑Transformer models, with a focus on avoiding off‑chip memory accesses. Key responsibilities include:Modeling data movement betweenSRAM and HBM/DRAMduring inference\r\nSweeping parameters such as:\r\nSRAM capacity\r\nContext length\r\nModel dimensions\r\nMapping thefeasibility boundarywhere inference can be performed fully on chip\r\nBreaking downper‑layer memory working sets\r\nIdentifyingwhen and why memory spills occur\r\nExploringtiling and scheduling strategiesto extend the no‑spill region\r\nValidating analytical results throughsimulation","company":"Brainchip","rawCompany":"brainchip","city":"Laguna Woods","state":"CA","isRemote":false,"isActive":false,"createdAt":"2026-04-10T04:50:44.514Z","occupations":[{"code":"17-2061.00","title":"Computer Hardware Engineers","slug":"computer-hardware-engineers"},{"code":"15-1299.08","title":"Computer Systems Engineers/Architects","slug":"computer-systems-engineers-architects"},{"code":"15-1221.00","title":"Computer and Information Research Scientists","slug":"computer-and-information-research-scientists"}],"industries":[{"code":"334413","title":"Semiconductor and Related Device Manufacturing","slug":"semiconductor-and-related-device-manufacturing"},{"code":"334111","title":"Electronic Computer Manufacturing","slug":"electronic-computer-manufacturing"},{"code":"541512","title":"Computer Systems Design Services","slug":"computer-systems-design-services"}],"jobPosting":{"@context":"https://schema.org","@type":"JobPosting","title":"Machine Learning Systems Intern","description":"Hybrid SSM‑Transformer models have a unique advantage for on‑chip memory efficiency:SSM layerscompress sequence history into a fixed‑size recurrent state\r\nAttention layersstore key‑value caches that grow with context lengthThis leads to an important design question:\r\nFor a given model configuration and maximum context length, can on‑chip SRAM be sized so that inference runs entirely on chip—eliminating the need for slower off‑chip HBM or DRAM?What the intern will work on:The intern will model and analyze memory behavior during inference of hybrid SSM‑Transformer models, with a focus on avoiding off‑chip memory accesses. Key responsibilities include:Modeling data movement betweenSRAM and HBM/DRAMduring inference\r\nSweeping parameters such as:\r\nSRAM capacity\r\nContext length\r\nModel dimensions\r\nMapping thefeasibility boundarywhere inference can be performed fully on chip\r\nBreaking downper‑layer memory working sets\r\nIdentifyingwhen and why memory spills occur\r\nExploringtiling and scheduling strategiesto extend the no‑spill region\r\nValidating analytical results throughsimulation","datePosted":"2026-04-10T04:50:44.514Z","dateModified":"2026-04-10T04:50:44.514Z","hiringOrganization":{"@type":"Organization","name":"Brainchip","sameAs":"https://jobsearcher.com"},"jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Laguna Woods","addressRegion":"CA","addressCountry":"US"}},"identifier":{"@type":"PropertyValue","name":"JobSearcher","value":"74954d2e40f4fc3dadc13ea7"},"url":"https://jobsearcher.com/jobs/74954d2e40f4fc3dadc13ea7"}}