{"schemaVersion":"jobsearcher.job.v1","id":"6cf5c85219c66d2a336ee607","url":"https://jobsearcher.com/jobs/6cf5c85219c66d2a336ee607","canonicalUrl":"https://jobsearcher.com/jobs/6cf5c85219c66d2a336ee607","title":"Application Specific Integrated Circuit Design Engineer","description":"We’re representing a venture-backed silicon photonics startup building high-performance systems for next-generation AI infrastructure.They’re looking for an ASIC/Digital Design Engineer to help architect and implement high-bandwidth silicon systems that connect compute logic with optically coupled memory and chiplet-based architectures.Experience with:ASIC digital design (RTL in Verilog / SystemVerilog) with tapeout experience in advanced nodes (e.g., 7nm and below preferred)Microarchitecture design of high-performance digital systems (pipelines, interconnects, memory hierarchies)High-speed data movement architectures (NoC, interconnect fabrics, streaming datapaths)High-speed I/O interfaces (PCIe, Ethernet, CXL, SERDES, DDR/HBM, or similar)Memory subsystem design (coherence, buffering, latency optimization, bandwidth scaling)ASIC integration across multiple IP blocks (3rd party IP, internal subsystems, interface bridging)Timing closure, PPA tradeoffs (power, performance, area) in large-scale SoCs or chiplet-based designsSystem-level thinking across compute + interconnect + memory boundariesNice to have:Experience with chiplet architectures or multi-die / heterogeneous integrationBackground in network processors, AI accelerators, or HPC-class SoCsExposure to optical interconnects, silicon photonics, or high-speed SerDes ecosystemsExperience bridging RTL ↔ physical design awareness (timing, floorplanning constraints, congestion-driven architecture decisions)Exposure to AI/ML workloads from a hardware efficiency / data movement perspective (not algorithm development)Remote-friendly (US) with preference for Bay Area proximity.","company":"Onyx","rawCompany":"onyx","city":"Augusta","state":"GA","isRemote":false,"isActive":true,"createdAt":"2026-10-06T04:45:55.831Z","occupations":[{"code":"17-2061.00","title":"Computer Hardware Engineers","slug":"computer-hardware-engineers"},{"code":"17-2072.00","title":"Electronics Engineers, Except Computer","slug":"electronics-engineers-except-computer"},{"code":"17-2199.00","title":"Engineers, All Other","slug":"engineers-all-other"}],"industries":[{"code":"334413","title":"Semiconductor and Related Device Manufacturing","slug":"semiconductor-and-related-device-manufacturing"},{"code":"334419","title":"Other Electronic Component Manufacturing","slug":"other-electronic-component-manufacturing"},{"code":"333242","title":"Semiconductor Machinery Manufacturing","slug":"semiconductor-machinery-manufacturing"}],"jobPosting":{"@context":"https://schema.org","@type":"JobPosting","title":"Application Specific Integrated Circuit Design Engineer","description":"We’re representing a venture-backed silicon photonics startup building high-performance systems for next-generation AI infrastructure.They’re looking for an ASIC/Digital Design Engineer to help architect and implement high-bandwidth silicon systems that connect compute logic with optically coupled memory and chiplet-based architectures.Experience with:ASIC digital design (RTL in Verilog / SystemVerilog) with tapeout experience in advanced nodes (e.g., 7nm and below preferred)Microarchitecture design of high-performance digital systems (pipelines, interconnects, memory hierarchies)High-speed data movement architectures (NoC, interconnect fabrics, streaming datapaths)High-speed I/O interfaces (PCIe, Ethernet, CXL, SERDES, DDR/HBM, or similar)Memory subsystem design (coherence, buffering, latency optimization, bandwidth scaling)ASIC integration across multiple IP blocks (3rd party IP, internal subsystems, interface bridging)Timing closure, PPA tradeoffs (power, performance, area) in large-scale SoCs or chiplet-based designsSystem-level thinking across compute + interconnect + memory boundariesNice to have:Experience with chiplet architectures or multi-die / heterogeneous integrationBackground in network processors, AI accelerators, or HPC-class SoCsExposure to optical interconnects, silicon photonics, or high-speed SerDes ecosystemsExperience bridging RTL ↔ physical design awareness (timing, floorplanning constraints, congestion-driven architecture decisions)Exposure to AI/ML workloads from a hardware efficiency / data movement perspective (not algorithm development)Remote-friendly (US) with preference for Bay Area proximity.","datePosted":"2026-10-06T04:45:55.831Z","dateModified":"2026-10-06T04:45:55.831Z","hiringOrganization":{"@type":"Organization","name":"Onyx","sameAs":"https://jobsearcher.com"},"jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Augusta","addressRegion":"GA","addressCountry":"US"}},"identifier":{"@type":"PropertyValue","name":"JobSearcher","value":"6cf5c85219c66d2a336ee607"},"url":"https://jobsearcher.com/jobs/6cf5c85219c66d2a336ee607"}}