{"schemaVersion":"jobsearcher.job.v1","id":"6864b2b3090d07f451f052b5","url":"https://jobsearcher.com/jobs/6864b2b3090d07f451f052b5","canonicalUrl":"https://jobsearcher.com/jobs/6864b2b3090d07f451f052b5","title":"DFT Design Engineer","description":"Job Details:\nJob Description:\nWe are seeking a senior skilled DFT Design Engineer to develop and implement comprehensive Design for Test solutions across our semiconductor products. This role involves RTL design, verification, and manufacturing support for various DFx methodologies including SCAN, MBIST, and BSCAN implementations. We are seeking a highly skilled DFT Design Engineer to join our semiconductor engineering team and drive the development of cutting-edge Design for Test solutions across our product portfolio. This critical role combines deep technical expertise in digital design with specialized knowledge of test methodologies to ensure our silicon products meet the highest quality standards for high-volume manufacturing.\nAs a Senior DFT Design Engineer, you will be responsible for architecting, implementing, and optimizing comprehensive test strategies that span from initial RTL development through production manufacturing. You will work at the intersection of design and test, collaborating with cross-functional teams including architecture, verification, physical design, and manufacturing to deliver robust DFT solutions that enable efficient testing while meeting stringent power, performance, and area requirements. The successful candidate will have extensive experience in DFT methodologies and will play a pivotal role in defining test architectures for complex SoCs, developing innovative solutions to challenging testability problems, and ensuring seamless integration of DFT features across multiple design hierarchies.\nThis position offers the opportunity to work on industry-leading semiconductor products and contribute to the advancement of DFT technologies in next-generation computing platforms. This role involves RTL design, verification, and manufacturing support for various DFx methodologies including SCAN, MBIST, and BSCAN implementations, with a focus on achieving optimal test coverage, minimizing defect escape rates, and reducing overall test costs while maintaining design integrity and performance targets.\nKey Responsibilities\nDesign & Development:\nDevelops logic design, register transfer level (RTL) coding, and simulation for DFT implementations\nProvides DFT timing closure support and generates test content for manufacturing delivery\nImplements various DFx content including SCAN, MBIST, and BSCAN methodologies\nApplies strategies, tools, and methods to write and generate RTL and structural code for DFT integration\nArchitecture & Collaboration:\nParticipates in defining architecture and microarchitecture features for blocks, subsystems, and SoCs\nCollaborates on DFT design including TAP, SCAN, MBIST, BSCAN, processor monitors, and in-system test/BIST\nIntegrates DFT blocks into functional IP and SoC while supporting customer integration requirements\nOptimization & Verification:\nOptimizes logic design to meet power, performance, area, timing, test coverage, DPM, and test time/vector memory reduction goals\nReviews verification plans and drives DFT design verification to achieve architecture specifications\nEnsures design features are verified correctly and implements corrective measures for failing RTL tests\nManufacturing & Production Support:\nDevelops HVM (High Volume Manufacturing) content for rapid bring-up and production ramp on ATE (Automatic Test Equipment)\nCollaborates with post-silicon and manufacturing teams for silicon verification and debug support\nDrives high test coverage through structural and IP-specific tests to achieve quality and DPM objectives\nDocuments learnings and improvement requirements for design and validation processes\nQualifications:\nMinimum Qualifications\nEducation & Experience:\nBachelor's degree in Electrical Engineering, Computer Science, or related field with 4+ years of industry experience or Master's degree in Electrical Engineering, Computer Science, or related field with 3+ years of industry experience\nTechnical Requirements:\n5+ years of hands-on experience with DFT (Design for Test) methodologies\n5+ years of experience with Array Test including MBIST (Memory Built-In Self-Test)\nExperience in RTL coding, simulation, and verification\nExperience in semiconductor manufacturing test processes and ATE systems\nPreferred Qualifications\nExpert-level proficiency in Tessent DFT tool suite\nAdvanced expertise in PrimeTime, specifically with DFT constraints and timing analysis\nExperience with additional DFT tools and methodologies\nKnowledge of advanced test compression techniques and fault models\nExperience with SoC-level DFT integration and customer support\nBackground in post-silicon validation and debug\nFamiliarity with industry test standards and protocols\nExperience in test cost optimization and DPM improvement initiatives\n\nJob Type:\nExperienced Hire\nShift:\nShift 1 (United States of America)\nPrimary Location:\nUS, Arizona, Phoenix\nAdditional Locations:\nUS, California, Santa Clara, US, Massachusetts, Beaver Brook, US, Oregon, Hillsboro, US, Texas, Austin\nBusiness group:\nAt the Data Center Group (DCG), we're committed to delivering exceptional products and delighting our customers. We offer both broad-market Xeon-based solutions and custom x86-based products, ensuring tailored innovation for diverse needs across general-purpose compute, web services, HPC, and AI-accelerated systems. Our charter encompasses defining business strategy and roadmaps, product management, developing ecosystems and business opportunities, delivering strong financial performance, and reinvigorating x86 leadership. Join us as we transform the data center segment through workload driven leadership products and close collaboration with our partners.\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nBenefits\nWe offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel .\n\nAnnual Salary Range for jobs which could be performed in the US: $141,910.00-269,100.00 USD\n\nThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.\n\nWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.\nADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.","company":"Intel","rawCompany":"intel","city":"Phoenix","state":"AZ","isRemote":false,"isActive":false,"createdAt":"2026-04-14T10:54:01.211Z","occupations":[{"code":"17-2072.00","title":"Electronics Engineers, Except Computer","slug":"electronics-engineers-except-computer"},{"code":"17-2061.00","title":"Computer Hardware Engineers","slug":"computer-hardware-engineers"},{"code":"17-2199.00","title":"Engineers, All Other","slug":"engineers-all-other"}],"industries":[{"code":"334413","title":"Semiconductor and Related Device Manufacturing","slug":"semiconductor-and-related-device-manufacturing"},{"code":"334419","title":"Other Electronic Component Manufacturing","slug":"other-electronic-component-manufacturing"},{"code":"333242","title":"Semiconductor Machinery Manufacturing","slug":"semiconductor-machinery-manufacturing"}],"jobPosting":{"@context":"https://schema.org","@type":"JobPosting","title":"DFT Design Engineer","description":"Job Details:\nJob Description:\nWe are seeking a senior skilled DFT Design Engineer to develop and implement comprehensive Design for Test solutions across our semiconductor products. This role involves RTL design, verification, and manufacturing support for various DFx methodologies including SCAN, MBIST, and BSCAN implementations. We are seeking a highly skilled DFT Design Engineer to join our semiconductor engineering team and drive the development of cutting-edge Design for Test solutions across our product portfolio. This critical role combines deep technical expertise in digital design with specialized knowledge of test methodologies to ensure our silicon products meet the highest quality standards for high-volume manufacturing.\nAs a Senior DFT Design Engineer, you will be responsible for architecting, implementing, and optimizing comprehensive test strategies that span from initial RTL development through production manufacturing. You will work at the intersection of design and test, collaborating with cross-functional teams including architecture, verification, physical design, and manufacturing to deliver robust DFT solutions that enable efficient testing while meeting stringent power, performance, and area requirements. The successful candidate will have extensive experience in DFT methodologies and will play a pivotal role in defining test architectures for complex SoCs, developing innovative solutions to challenging testability problems, and ensuring seamless integration of DFT features across multiple design hierarchies.\nThis position offers the opportunity to work on industry-leading semiconductor products and contribute to the advancement of DFT technologies in next-generation computing platforms. This role involves RTL design, verification, and manufacturing support for various DFx methodologies including SCAN, MBIST, and BSCAN implementations, with a focus on achieving optimal test coverage, minimizing defect escape rates, and reducing overall test costs while maintaining design integrity and performance targets.\nKey Responsibilities\nDesign & Development:\nDevelops logic design, register transfer level (RTL) coding, and simulation for DFT implementations\nProvides DFT timing closure support and generates test content for manufacturing delivery\nImplements various DFx content including SCAN, MBIST, and BSCAN methodologies\nApplies strategies, tools, and methods to write and generate RTL and structural code for DFT integration\nArchitecture & Collaboration:\nParticipates in defining architecture and microarchitecture features for blocks, subsystems, and SoCs\nCollaborates on DFT design including TAP, SCAN, MBIST, BSCAN, processor monitors, and in-system test/BIST\nIntegrates DFT blocks into functional IP and SoC while supporting customer integration requirements\nOptimization & Verification:\nOptimizes logic design to meet power, performance, area, timing, test coverage, DPM, and test time/vector memory reduction goals\nReviews verification plans and drives DFT design verification to achieve architecture specifications\nEnsures design features are verified correctly and implements corrective measures for failing RTL tests\nManufacturing & Production Support:\nDevelops HVM (High Volume Manufacturing) content for rapid bring-up and production ramp on ATE (Automatic Test Equipment)\nCollaborates with post-silicon and manufacturing teams for silicon verification and debug support\nDrives high test coverage through structural and IP-specific tests to achieve quality and DPM objectives\nDocuments learnings and improvement requirements for design and validation processes\nQualifications:\nMinimum Qualifications\nEducation & Experience:\nBachelor's degree in Electrical Engineering, Computer Science, or related field with 4+ years of industry experience or Master's degree in Electrical Engineering, Computer Science, or related field with 3+ years of industry experience\nTechnical Requirements:\n5+ years of hands-on experience with DFT (Design for Test) methodologies\n5+ years of experience with Array Test including MBIST (Memory Built-In Self-Test)\nExperience in RTL coding, simulation, and verification\nExperience in semiconductor manufacturing test processes and ATE systems\nPreferred Qualifications\nExpert-level proficiency in Tessent DFT tool suite\nAdvanced expertise in PrimeTime, specifically with DFT constraints and timing analysis\nExperience with additional DFT tools and methodologies\nKnowledge of advanced test compression techniques and fault models\nExperience with SoC-level DFT integration and customer support\nBackground in post-silicon validation and debug\nFamiliarity with industry test standards and protocols\nExperience in test cost optimization and DPM improvement initiatives\n\nJob Type:\nExperienced Hire\nShift:\nShift 1 (United States of America)\nPrimary Location:\nUS, Arizona, Phoenix\nAdditional Locations:\nUS, California, Santa Clara, US, Massachusetts, Beaver Brook, US, Oregon, Hillsboro, US, Texas, Austin\nBusiness group:\nAt the Data Center Group (DCG), we're committed to delivering exceptional products and delighting our customers. We offer both broad-market Xeon-based solutions and custom x86-based products, ensuring tailored innovation for diverse needs across general-purpose compute, web services, HPC, and AI-accelerated systems. Our charter encompasses defining business strategy and roadmaps, product management, developing ecosystems and business opportunities, delivering strong financial performance, and reinvigorating x86 leadership. Join us as we transform the data center segment through workload driven leadership products and close collaboration with our partners.\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nBenefits\nWe offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel .\n\nAnnual Salary Range for jobs which could be performed in the US: $141,910.00-269,100.00 USD\n\nThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.\n\nWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.\nADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.","datePosted":"2026-04-14T10:54:01.211Z","dateModified":"2026-04-14T10:54:01.211Z","hiringOrganization":{"@type":"Organization","name":"Intel","sameAs":"https://jobsearcher.com"},"jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Phoenix","addressRegion":"AZ","addressCountry":"US"}},"identifier":{"@type":"PropertyValue","name":"JobSearcher","value":"6864b2b3090d07f451f052b5"},"url":"https://jobsearcher.com/jobs/6864b2b3090d07f451f052b5"}}