{"schemaVersion":"jobsearcher.job.v1","id":"68045ff3bd17520310d3e5c9","url":"https://jobsearcher.com/jobs/68045ff3bd17520310d3e5c9","canonicalUrl":"https://jobsearcher.com/jobs/68045ff3bd17520310d3e5c9","title":"FPGA Engineer Engineer (eInfochips)","description":"Location San Jose CA and Austin TX (Day-1 Onsite)\n\nExperience 9+ Years\n\nResponsibilities\nProficient in Verilog/System Verilog coding constructs.\n\nKnowledge of front-end tools (Verilog simulators, connectivity tools, CDC checkers, low power static checkers, linting).\n\nExperience with high speed PCIe designs and protocols.\n\nExperience with industry standard interface protocols such as AXI, APB, etc.\n\nExperience with ARM Fabric IPs.\n\nExperience with IPXACT.\n\nUnderstanding of computer architecture fundamentals.\n\nAbility to write scripts using Python, Tcl, Perl, etc.\n\nExperience with EDA tools such as VCS, VCLP, Spyglass Lint, Questa CDC, Fusion Compiler, Design Compiler, Genus.\n\nProficiency with UPF (low power intent).\n\nProficiency in clock crossing techniques.\n\nKnowledge of static timing analysis and timing signoff fundamentals.\n\nQualifications\nStrong understanding of RTL design and digital concepts.\n\nStrong experience with EDA tools: Fusion Compiler, CDC.\n\nProficient scripting: Perl, Python, TCL.\n\nAt least 5+ years of experience in Verilog design.\n\nExperience with AMBA AXI bus and ARM or C based processor.\n\nCustomer‑focused: ensure customer satisfaction.\n\nEffective reporting to customers on daily or weekly progress.\n\nWork Arrangement Fully onsite: Must be able to travel to an Arrow client office location as requested by Arrow client leadership.\n\nEEO Statement Arrow is an equal opportunity employer. All applicants will be considered for employment without attention to race, color, religion, gender, age, sexual orientation, gender identity, national origin, veteran or disability status.\n\n#J-18808-Ljbffr","company":"Einfochips","rawCompany":"einfochips","city":"Austin","state":"TX","isRemote":false,"isActive":false,"createdAt":"2026-06-21T03:19:29.529Z","occupations":[{"code":"17-2072.00","title":"Electronics Engineers, Except Computer","slug":"electronics-engineers-except-computer"},{"code":"17-2061.00","title":"Computer Hardware Engineers","slug":"computer-hardware-engineers"},{"code":"17-2199.00","title":"Engineers, All Other","slug":"engineers-all-other"}],"industries":[{"code":"334413","title":"Semiconductor and Related Device Manufacturing","slug":"semiconductor-and-related-device-manufacturing"},{"code":"541512","title":"Computer Systems Design Services","slug":"computer-systems-design-services"},{"code":"334111","title":"Electronic Computer Manufacturing","slug":"electronic-computer-manufacturing"}],"jobPosting":{"@context":"https://schema.org","@type":"JobPosting","title":"FPGA Engineer Engineer (eInfochips)","description":"Location San Jose CA and Austin TX (Day-1 Onsite)\n\nExperience 9+ Years\n\nResponsibilities\nProficient in Verilog/System Verilog coding constructs.\n\nKnowledge of front-end tools (Verilog simulators, connectivity tools, CDC checkers, low power static checkers, linting).\n\nExperience with high speed PCIe designs and protocols.\n\nExperience with industry standard interface protocols such as AXI, APB, etc.\n\nExperience with ARM Fabric IPs.\n\nExperience with IPXACT.\n\nUnderstanding of computer architecture fundamentals.\n\nAbility to write scripts using Python, Tcl, Perl, etc.\n\nExperience with EDA tools such as VCS, VCLP, Spyglass Lint, Questa CDC, Fusion Compiler, Design Compiler, Genus.\n\nProficiency with UPF (low power intent).\n\nProficiency in clock crossing techniques.\n\nKnowledge of static timing analysis and timing signoff fundamentals.\n\nQualifications\nStrong understanding of RTL design and digital concepts.\n\nStrong experience with EDA tools: Fusion Compiler, CDC.\n\nProficient scripting: Perl, Python, TCL.\n\nAt least 5+ years of experience in Verilog design.\n\nExperience with AMBA AXI bus and ARM or C based processor.\n\nCustomer‑focused: ensure customer satisfaction.\n\nEffective reporting to customers on daily or weekly progress.\n\nWork Arrangement Fully onsite: Must be able to travel to an Arrow client office location as requested by Arrow client leadership.\n\nEEO Statement Arrow is an equal opportunity employer. All applicants will be considered for employment without attention to race, color, religion, gender, age, sexual orientation, gender identity, national origin, veteran or disability status.\n\n#J-18808-Ljbffr","datePosted":"2026-06-21T03:19:29.529Z","dateModified":"2026-06-21T03:19:29.529Z","hiringOrganization":{"@type":"Organization","name":"Einfochips","sameAs":"https://jobsearcher.com"},"jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Austin","addressRegion":"TX","addressCountry":"US"}},"identifier":{"@type":"PropertyValue","name":"JobSearcher","value":"68045ff3bd17520310d3e5c9"},"url":"https://jobsearcher.com/jobs/68045ff3bd17520310d3e5c9"}}