{"schemaVersion":"jobsearcher.job.v1","id":"5e20936cb4275bbb50f13bea","url":"https://jobsearcher.com/jobs/5e20936cb4275bbb50f13bea","canonicalUrl":"https://jobsearcher.com/jobs/5e20936cb4275bbb50f13bea","title":"Implementation Engineer - Engineer, Staff","description":"Title: Implementation Engineer - Engineer, StaffLocation: Santa Clara CA / Austin TX / San Diego CAWe are looking for a Staff-level technical expert to drive synthesis, timing, PPA optimization, and RTL-to-implementation readiness for complex, high-performance SoCs. What You’ll Do:• Lead synthesis and optimization for complex SoC blocks and subsystems.• Drive performance, power, area (PPA), and Fmax convergence.• Own Formal Verification (FV) and Formal Equivalence/LEC methodology and closure.• Debug RTL-to-netlist and netlist-to-netlist equivalence failures across synthesis and ECO stages.• Drive formal verification and closure• Analyze critical paths and identify RTL, architecture, constraint, and implementation bottlenecks.• Develop and review SDC constraints, clocks, timing exceptions, and MMMC scenarios.• Drive physically aware synthesis and synthesis-to-P&R correlation.• Partner with RTL, FV, STA, Physical Design, DFT, and architecture teams.• Debug timing, congestion, clocking, high-fanout, QoR, and equivalence issues.• Develop scalable synthesis, FV, timing, and QoR methodologies and automation.• Lead technical reviews, and drive complex problems to closureWhat We’re Looking For:• Strong ASIC/SoC background in synthesis, formal verification, STA, RTL optimization, or physical implementation.• 7 years of experience• Experience with Fusion Compiler, Design Compiler, Genus, Conformal LEC, Formality, PrimeTime. • Strong understanding of FV/LEC, STA, SDC, MMMC, clocking, low-power/UPF, and implementation flows.• Experience driving timing, PPA, and equivalence closure on large SoCs.• Strong Tcl/Python automation and cross-functional technical leadership skills. Education and Experience:• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.OR PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.Job Description As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with crossfunctional groups to determine product execution path. Principal Duties & Responsibilities:• Leverages advanced ASIC knowledge and experience to define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power products.• Creates advanced architectures, circuit specifications, logic designs, and/or system simulations based on system-level requirements.• Collaborates across functional teams (e.g., software architecture, hardware architecture, product management, program management teams) to develop and execute an implementation strategy that meets system requirements and customer needs.• Evaluates all aspects of complex process flow from high-level design to synthesis, place and route, timing and power use, and verification or similarly for custom circuit design/layout flow.• Utilizes tools/applications (e.g., RTL to GDS Flow, Virtuoso) to execute and enable advanced architecture and design of multiple complex blocks/SoC or IC Packages.• Writes and reviews detailed technical documentation for complex EDA/IP/ASIC projects.Level of Responsibility:• Works independently with minimal supervision.• Provides supervision/guidance to other team members.• Decision-making is significant in nature and affects work beyond immediate work group.• Requires verbal and written communication skills to convey complex information. May require negotiation, influence, tact, etc.• Has a moderate amount of influence over key organizational decisions (e.g., is consulted by senior leadership to make key decisions).• Tasks do not have defined steps; planning, problem-solving, and prioritization must occur to complete the tasks effectively.","company":"Thundersoft","rawCompany":"thundersoft","city":"San Jose","state":"CA","isRemote":false,"isActive":false,"createdAt":"2026-11-13T09:16:25.214Z","occupations":[{"code":"17-2112.02","title":"Validation Engineers","slug":"validation-engineers"},{"code":"17-2072.00","title":"Electronics Engineers, Except Computer","slug":"electronics-engineers-except-computer"},{"code":"17-2199.00","title":"Engineers, All Other","slug":"engineers-all-other"}],"industries":[{"code":"334413","title":"Semiconductor and Related Device Manufacturing","slug":"semiconductor-and-related-device-manufacturing"},{"code":"334419","title":"Other Electronic Component Manufacturing","slug":"other-electronic-component-manufacturing"},{"code":"541715","title":"Research and Development in the Physical, Engineering, and Life Sciences (except Nanotechnology and Biotechnology)","slug":"research-and-development-in-the-physical-engineering-and-life-sciences-except-nanotechnology-and-biotechnology"}],"jobPosting":{"@context":"https://schema.org","@type":"JobPosting","title":"Implementation Engineer - Engineer, Staff","description":"Title: Implementation Engineer - Engineer, StaffLocation: Santa Clara CA / Austin TX / San Diego CAWe are looking for a Staff-level technical expert to drive synthesis, timing, PPA optimization, and RTL-to-implementation readiness for complex, high-performance SoCs. What You’ll Do:• Lead synthesis and optimization for complex SoC blocks and subsystems.• Drive performance, power, area (PPA), and Fmax convergence.• Own Formal Verification (FV) and Formal Equivalence/LEC methodology and closure.• Debug RTL-to-netlist and netlist-to-netlist equivalence failures across synthesis and ECO stages.• Drive formal verification and closure• Analyze critical paths and identify RTL, architecture, constraint, and implementation bottlenecks.• Develop and review SDC constraints, clocks, timing exceptions, and MMMC scenarios.• Drive physically aware synthesis and synthesis-to-P&R correlation.• Partner with RTL, FV, STA, Physical Design, DFT, and architecture teams.• Debug timing, congestion, clocking, high-fanout, QoR, and equivalence issues.• Develop scalable synthesis, FV, timing, and QoR methodologies and automation.• Lead technical reviews, and drive complex problems to closureWhat We’re Looking For:• Strong ASIC/SoC background in synthesis, formal verification, STA, RTL optimization, or physical implementation.• 7 years of experience• Experience with Fusion Compiler, Design Compiler, Genus, Conformal LEC, Formality, PrimeTime. • Strong understanding of FV/LEC, STA, SDC, MMMC, clocking, low-power/UPF, and implementation flows.• Experience driving timing, PPA, and equivalence closure on large SoCs.• Strong Tcl/Python automation and cross-functional technical leadership skills. Education and Experience:• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.OR PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.Job Description As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with crossfunctional groups to determine product execution path. Principal Duties & Responsibilities:• Leverages advanced ASIC knowledge and experience to define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power products.• Creates advanced architectures, circuit specifications, logic designs, and/or system simulations based on system-level requirements.• Collaborates across functional teams (e.g., software architecture, hardware architecture, product management, program management teams) to develop and execute an implementation strategy that meets system requirements and customer needs.• Evaluates all aspects of complex process flow from high-level design to synthesis, place and route, timing and power use, and verification or similarly for custom circuit design/layout flow.• Utilizes tools/applications (e.g., RTL to GDS Flow, Virtuoso) to execute and enable advanced architecture and design of multiple complex blocks/SoC or IC Packages.• Writes and reviews detailed technical documentation for complex EDA/IP/ASIC projects.Level of Responsibility:• Works independently with minimal supervision.• Provides supervision/guidance to other team members.• Decision-making is significant in nature and affects work beyond immediate work group.• Requires verbal and written communication skills to convey complex information. May require negotiation, influence, tact, etc.• Has a moderate amount of influence over key organizational decisions (e.g., is consulted by senior leadership to make key decisions).• Tasks do not have defined steps; planning, problem-solving, and prioritization must occur to complete the tasks effectively.","datePosted":"2026-11-13T09:16:25.214Z","dateModified":"2026-11-13T09:16:25.214Z","hiringOrganization":{"@type":"Organization","name":"Thundersoft","sameAs":"https://jobsearcher.com"},"jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"San Jose","addressRegion":"CA","addressCountry":"US"}},"identifier":{"@type":"PropertyValue","name":"JobSearcher","value":"5e20936cb4275bbb50f13bea"},"url":"https://jobsearcher.com/jobs/5e20936cb4275bbb50f13bea"}}