{"schemaVersion":"jobsearcher.job.v1","id":"5db5119896e4fbefa2afe5ac","url":"https://jobsearcher.com/jobs/5db5119896e4fbefa2afe5ac","canonicalUrl":"https://jobsearcher.com/jobs/5db5119896e4fbefa2afe5ac","title":"DV Engineer","description":"Senior ASIC/SoC Design Verification Engineer (Chip-Level Verification)\n\nAn outstanding, full-time opening is available in Silicon Valley, CA for an experienced ASIC/SoC Design Verification Engineer with deep expertise in chip-level verification of complex SoCs and multi-IP integrated systems.\n\nThis role requires proven experience owning end-to-end pre-silicon verification from planning through coverage closure and tapeout readiness in a high-performance engineering environment. This is a fully onsite role (5 days/week) in the South Bay Area. Compensation up to $225K DOE + strong benefits + long-term project stability\n\nAll candidates MUST have the following experiences to qualify for consideration:\n\n8+ years of ASIC/SoC Design Verification experience with significant chip-level verification exposure\nExtensive chip-level / full SoC verification ownership, including planning, execution, and closure of verification for complex multi-IP SoCs\nStrong hands-on experience developing and maintaining SystemVerilog/UVM-based verification environments, including drivers, monitors, scoreboards, sequences, agents, and coverage models\nExperience defining and executing verification plans (vPlan) and coverage-driven verification strategies\nStrong expertise in functional, code, assertion (SVA), and toggle coverage closure\nHands-on experience with debugging RTL and verification environments, including root-cause failure analysis\nExperience with regression planning, execution, and failure triage at chip-level scale\nStrong experience with AMBA protocols (AXI, AHB, APB) and multi-IP subsystem integration\nExperience with industry-standard simulators such as Synopsys VCS, Cadence Xcelium, or Siemens Questa\nExperience developing test cases, checkers, scoreboards, and coverage models\nExperience collaborating with Design, Architecture, Firmware, and Post-Silicon teams\nExperience collaborating closely with Design, Architecture, Firmware, and Post-Silicon teams\nProven experience supporting successful ASIC/SoC tapeouts\nBachelor’s or Master’s Degree in Electrical Engineering, Computer Science, or related field\nMust be able to work onsite 5 days/week in Silicon Valley\n\nIf interested and QUALIFIED, please send resume in Microsoft Word format to: krissid@etechhi.com\n\nEtech Hi, Inc. is an equal opportunity employer/staffing firm and we are committed to providing a workplace free from harassment and discrimination. We celebrate the unique differences of our employees and candidates because that is what drives curiosity, innovation, and the success of our business. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, gender identity or expression, age, marital status, veteran status, disability status, pregnancy, parental status, genetic information, political affiliation, or any other status protected by the laws or regulations in the locations where we operate.\n\n#ZR","company":"Etech","rawCompany":"etech","city":"Milpitas","state":"CA","isRemote":false,"isActive":false,"createdAt":"2026-08-04T19:26:52.779Z","occupations":[{"code":"17-2112.02","title":"Validation Engineers","slug":"validation-engineers"},{"code":"17-2072.00","title":"Electronics Engineers, Except Computer","slug":"electronics-engineers-except-computer"},{"code":"17-2061.00","title":"Computer Hardware Engineers","slug":"computer-hardware-engineers"}],"industries":[{"code":"334413","title":"Semiconductor and Related Device Manufacturing","slug":"semiconductor-and-related-device-manufacturing"},{"code":"334419","title":"Other Electronic Component Manufacturing","slug":"other-electronic-component-manufacturing"},{"code":"333242","title":"Semiconductor Machinery Manufacturing","slug":"semiconductor-machinery-manufacturing"}],"jobPosting":{"@context":"https://schema.org","@type":"JobPosting","title":"DV Engineer","description":"Senior ASIC/SoC Design Verification Engineer (Chip-Level Verification)\n\nAn outstanding, full-time opening is available in Silicon Valley, CA for an experienced ASIC/SoC Design Verification Engineer with deep expertise in chip-level verification of complex SoCs and multi-IP integrated systems.\n\nThis role requires proven experience owning end-to-end pre-silicon verification from planning through coverage closure and tapeout readiness in a high-performance engineering environment. This is a fully onsite role (5 days/week) in the South Bay Area. Compensation up to $225K DOE + strong benefits + long-term project stability\n\nAll candidates MUST have the following experiences to qualify for consideration:\n\n8+ years of ASIC/SoC Design Verification experience with significant chip-level verification exposure\nExtensive chip-level / full SoC verification ownership, including planning, execution, and closure of verification for complex multi-IP SoCs\nStrong hands-on experience developing and maintaining SystemVerilog/UVM-based verification environments, including drivers, monitors, scoreboards, sequences, agents, and coverage models\nExperience defining and executing verification plans (vPlan) and coverage-driven verification strategies\nStrong expertise in functional, code, assertion (SVA), and toggle coverage closure\nHands-on experience with debugging RTL and verification environments, including root-cause failure analysis\nExperience with regression planning, execution, and failure triage at chip-level scale\nStrong experience with AMBA protocols (AXI, AHB, APB) and multi-IP subsystem integration\nExperience with industry-standard simulators such as Synopsys VCS, Cadence Xcelium, or Siemens Questa\nExperience developing test cases, checkers, scoreboards, and coverage models\nExperience collaborating with Design, Architecture, Firmware, and Post-Silicon teams\nExperience collaborating closely with Design, Architecture, Firmware, and Post-Silicon teams\nProven experience supporting successful ASIC/SoC tapeouts\nBachelor’s or Master’s Degree in Electrical Engineering, Computer Science, or related field\nMust be able to work onsite 5 days/week in Silicon Valley\n\nIf interested and QUALIFIED, please send resume in Microsoft Word format to: krissid@etechhi.com\n\nEtech Hi, Inc. is an equal opportunity employer/staffing firm and we are committed to providing a workplace free from harassment and discrimination. We celebrate the unique differences of our employees and candidates because that is what drives curiosity, innovation, and the success of our business. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, gender identity or expression, age, marital status, veteran status, disability status, pregnancy, parental status, genetic information, political affiliation, or any other status protected by the laws or regulations in the locations where we operate.\n\n#ZR","datePosted":"2026-08-04T19:26:52.779Z","dateModified":"2026-08-04T19:26:52.779Z","hiringOrganization":{"@type":"Organization","name":"Etech","sameAs":"https://jobsearcher.com"},"jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Milpitas","addressRegion":"CA","addressCountry":"US"}},"identifier":{"@type":"PropertyValue","name":"JobSearcher","value":"5db5119896e4fbefa2afe5ac"},"url":"https://jobsearcher.com/jobs/5db5119896e4fbefa2afe5ac"}}