{"schemaVersion":"jobsearcher.job.v1","id":"5cdff14049e5a66256dc986b","url":"https://jobsearcher.com/jobs/5cdff14049e5a66256dc986b","canonicalUrl":"https://jobsearcher.com/jobs/5cdff14049e5a66256dc986b","title":"Engineering, Principal Engineer","description":"The Hiring Manager is open to hiring in \"Austin\" and \"Sunnyvale\" both for this position.\n\nAs a member of the IP Digital Design Methodology team, you will work with global teams to define best in class ASIC design standards and flows and assist IP development teams. You will be involved with next generation SerDes and Memory interface controllers, PHYs, and subsystems.\nWe Are:\nAt Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.\nYou Are:\nYou are an experienced ASIC Digital Signoff Engineer with a deep passion for developing cutting-edge technology and direct hands-on experience with STA and EM/IR flows. With over 12+ years of hands-on experience, you have honed your skills in high-speed digital IP cores and/or SOCs development. You have a solid understanding of digital design flows and deep expertise in Static Timing Analysis (STA), Power Analysis, and EM/IR for advanced node designs. Your technical expertise is complemented by your ability to foster cross-functional collaboration, driving innovation and effective communication across global teams. Your analytical mind and problem-solving skills enable you to tackle complex challenges and deliver high-quality results. You are known for your clear and concise documentation, and your familiarity with Synopsys tools and high-speed interface protocols is a significant advantage.\nWhat You’ll Be Doing:\nDevelop and deploy advanced node signoff methodologies for cutting-edge IP designs targeting different foundries.\nWork with leading edge designs and teams to drive the industry-best PPA for IP designs.\nEvaluate and exercise various aspects of the development flow which include signoff timing, power, physical verification, EM/IR analysis, and ECO’s.\nDevelop and maintain best in class digital design methodologies, including documentation, scripts, and training materials.\nWork as a liaison between Synopsys tool and IP design teams.\nContinuously improve and refine design processes to enhance efficiency and performance.\nWhat You’ll Need:\nBS or MS in EE with 12+ years of hands-on experience developing CAD flows for high-speed digital IP cores and/or SOCs.\nDirect hands-on experience with enabling advanced node STA/ Timing signoff flows at SoC level.\nKnowledge of IP deliverables, ASIC implementation and physical design flow and tools, memories, logic libraries, and PDK versions.\nFamiliarity with EMIR & Thermal sign-off flows is a plus.\nAbility to facilitate cross-functional collaboration, including fostering innovation, improving communication, and driving results.\nGood analysis, debugging, and problem-solving skills.\nSolid written and verbal communication skills and the ability to create clear and concise documentation and provide training.\nFamiliarity with other Synopsys tools such as StarRC and ICV is a plus.\nWorking knowledge of high-speed interface protocols such as HDMI, MIPI, PCIe, SATA, Ethernet, USB, DP, and DDR are a plus.\nThe Impact You Will Have:\nDrive innovation in high-speed digital IP core and Subsystem development.\nEnhance the efficiency and effectiveness of our design and verification processes.\nContribute to the development of state-of-the-art technology that powers the next generation of intelligent systems.\nEnsure the highest quality standards in the design and implementation of our products.\nFacilitate seamless collaboration across global teams, fostering a culture of innovation and excellence.\nSupport the continuous improvement of our design methodologies and tools, staying at the forefront of industry advancements.\nWho You Are:\nYou are a collaborative and innovative engineer with a strong technical background and a passion for excellence. You thrive in a dynamic environment and enjoy working with global teams to achieve common goals. Your ability to communicate effectively and your commitment to continuous improvement make you an invaluable asset to our team.\nThe Team You’ll Be A Part Of:\nYou will join the Interface IP Digital Design Methodology team, working with global teams to define best practice ASIC design standards and flows. This team is dedicated to supporting IP development teams and is involved with next-generation SerDes and Memory interface controllers, PHYs, and subsystems.\n#LI-NK4","company":"Synopsys","rawCompany":"synopsys","city":"Sunnyvale","state":"CA","isRemote":false,"isActive":false,"createdAt":"2026-07-10T03:14:15.992Z","occupations":[{"code":"17-2072.00","title":"Electronics Engineers, Except Computer","slug":"electronics-engineers-except-computer"},{"code":"17-2199.00","title":"Engineers, All Other","slug":"engineers-all-other"},{"code":"17-2071.00","title":"Electrical Engineers","slug":"electrical-engineers"}],"industries":[{"code":"334413","title":"Semiconductor and Related Device Manufacturing","slug":"semiconductor-and-related-device-manufacturing"},{"code":"334419","title":"Other Electronic Component Manufacturing","slug":"other-electronic-component-manufacturing"},{"code":"334418","title":"Printed Circuit Assembly (Electronic Assembly) Manufacturing","slug":"printed-circuit-assembly-electronic-assembly-manufacturing"}],"jobPosting":{"@context":"https://schema.org","@type":"JobPosting","title":"Engineering, Principal Engineer","description":"The Hiring Manager is open to hiring in \"Austin\" and \"Sunnyvale\" both for this position.\n\nAs a member of the IP Digital Design Methodology team, you will work with global teams to define best in class ASIC design standards and flows and assist IP development teams. You will be involved with next generation SerDes and Memory interface controllers, PHYs, and subsystems.\nWe Are:\nAt Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.\nYou Are:\nYou are an experienced ASIC Digital Signoff Engineer with a deep passion for developing cutting-edge technology and direct hands-on experience with STA and EM/IR flows. With over 12+ years of hands-on experience, you have honed your skills in high-speed digital IP cores and/or SOCs development. You have a solid understanding of digital design flows and deep expertise in Static Timing Analysis (STA), Power Analysis, and EM/IR for advanced node designs. Your technical expertise is complemented by your ability to foster cross-functional collaboration, driving innovation and effective communication across global teams. Your analytical mind and problem-solving skills enable you to tackle complex challenges and deliver high-quality results. You are known for your clear and concise documentation, and your familiarity with Synopsys tools and high-speed interface protocols is a significant advantage.\nWhat You’ll Be Doing:\nDevelop and deploy advanced node signoff methodologies for cutting-edge IP designs targeting different foundries.\nWork with leading edge designs and teams to drive the industry-best PPA for IP designs.\nEvaluate and exercise various aspects of the development flow which include signoff timing, power, physical verification, EM/IR analysis, and ECO’s.\nDevelop and maintain best in class digital design methodologies, including documentation, scripts, and training materials.\nWork as a liaison between Synopsys tool and IP design teams.\nContinuously improve and refine design processes to enhance efficiency and performance.\nWhat You’ll Need:\nBS or MS in EE with 12+ years of hands-on experience developing CAD flows for high-speed digital IP cores and/or SOCs.\nDirect hands-on experience with enabling advanced node STA/ Timing signoff flows at SoC level.\nKnowledge of IP deliverables, ASIC implementation and physical design flow and tools, memories, logic libraries, and PDK versions.\nFamiliarity with EMIR & Thermal sign-off flows is a plus.\nAbility to facilitate cross-functional collaboration, including fostering innovation, improving communication, and driving results.\nGood analysis, debugging, and problem-solving skills.\nSolid written and verbal communication skills and the ability to create clear and concise documentation and provide training.\nFamiliarity with other Synopsys tools such as StarRC and ICV is a plus.\nWorking knowledge of high-speed interface protocols such as HDMI, MIPI, PCIe, SATA, Ethernet, USB, DP, and DDR are a plus.\nThe Impact You Will Have:\nDrive innovation in high-speed digital IP core and Subsystem development.\nEnhance the efficiency and effectiveness of our design and verification processes.\nContribute to the development of state-of-the-art technology that powers the next generation of intelligent systems.\nEnsure the highest quality standards in the design and implementation of our products.\nFacilitate seamless collaboration across global teams, fostering a culture of innovation and excellence.\nSupport the continuous improvement of our design methodologies and tools, staying at the forefront of industry advancements.\nWho You Are:\nYou are a collaborative and innovative engineer with a strong technical background and a passion for excellence. You thrive in a dynamic environment and enjoy working with global teams to achieve common goals. Your ability to communicate effectively and your commitment to continuous improvement make you an invaluable asset to our team.\nThe Team You’ll Be A Part Of:\nYou will join the Interface IP Digital Design Methodology team, working with global teams to define best practice ASIC design standards and flows. This team is dedicated to supporting IP development teams and is involved with next-generation SerDes and Memory interface controllers, PHYs, and subsystems.\n#LI-NK4","datePosted":"2026-07-10T03:14:15.992Z","dateModified":"2026-07-10T03:14:15.992Z","hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://jobsearcher.com"},"jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Sunnyvale","addressRegion":"CA","addressCountry":"US"}},"identifier":{"@type":"PropertyValue","name":"JobSearcher","value":"5cdff14049e5a66256dc986b"},"url":"https://jobsearcher.com/jobs/5cdff14049e5a66256dc986b"}}