{"schemaVersion":"jobsearcher.job.v1","id":"5c88f4f802060b4e05a45760","url":"https://jobsearcher.com/jobs/5c88f4f802060b4e05a45760","canonicalUrl":"https://jobsearcher.com/jobs/5c88f4f802060b4e05a45760","title":"Advanced Packaging Technology Pathfinding and Development Engineer","description":"About Marvell\nMarvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.\nAt Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.\nYour Team, Your Impact\nThe Marvell Advanced Packaging R&D team is responsible for package design and technology development to meet the electrical, mechanical, thermal and system requirements for the next generation high performance computing (HPC), Artificial Intelligence (AI) and networking solutions. The group focuses on signal integrity, power integrity, thermal integrity, mechanical integrity, processability, manufacturability, and reliability, involving high speed signaling and complex power delivery networks (PDNs) requiring innovative and custom solutions to meet constantly evolving customer needs. Many of the new designs require multi-chip, multiple component configurations involving, but not limited to, 2.5D and 3D packages, Co-packaged copper or optics and advanced substrates. Marvell has partnered with the world's leading manufacturers to solve our customer’s most challenging designs and integrations with industry-leading packaging technologies.\nWhat You Can Expect\nDevelop packaging technology roadmap for AI XPU, XPU-attach and Switch\nExplore technologies beyond what is currently available, make recommendations, and create and protect IP to maximize performance. Create new package technology concepts from open ended ideas, perform routing feasibility, signal and power integrity studies for design optimization. Explore technology feasibility and create proof-of-concept samples and productize technologies.\nDefine package architecture including chiplet topology, interposer/substrate scaling, power delivery network strategy, and thermal design envelope. Lead co-design efforts across silicon design, floorplanning, PDN modeling, and mechanical/thermal reliability. Lead package material selection, substrate stack-up definition, mechanical modeling, and reliability analysis. Partner with silicon design teams to co-optimize die floorplan, bump map, TSV, and RDL requirements.\nWork with OSATs / Foundry partners to evaluate process capability, manufacturability, yield, and cost. Drive package qualification and reliability validation to volume readiness.\nWhat We're Looking For\nExperience in advanced package and substrate technologies with deep understanding of process and materials, component and board level reliability, warpage and thermal management. Experience in managing substrate and assembly material vendors, substrate manufacturers, OSATs and foundries.\nDeep knowledge of Electrical Engineering concepts, circuit extractions and simulation, as well as design methodology and strategies. Experience in signal and power integrity simulations, analysis and optimization for 2.5D and 3D packages including interface with memory, interposer, substrates and PCBs. Ability to determine optimal signal routing, power delivery verification and package size determination\nBachelor’s degree in mechanical engineering, material science or related fields and 15+ years of related professional experience or master’s degree and 12+ years of related professional experience or PhD degree / post-doc with 8+ years of experience.\nExperience interfacing with product design teams for optimized floor-planning, package related design input and power delivery network design.\nBachelor's degree in electrical engineering or related fields and 15+ years of related professional experience in signal and power integrity, or master’s degree and 10+ years of related professional experience, or PhD degree with 8+ years of experience.\nSkills needed to be successful in this role:\nAbility to develop an idea into a proof of concept and then a proof of concept into a productizable technology\nDeep understanding of fundamental concepts of signal and power integrity, transmission line and electromigration, and the ability to apply those concepts to create new design rules and explore new technologies utilizing current baseline for 2.5D/3D package technology including (a) CoWoS-S/R/L, (b) EMIB-T, (c) CPO, (d) CPC.\nMastery in tools and workflows to guide and enable the team on what sims need to be run: previous hands-on experience with signal and power integrity analyses using Cadence Sigrity PowerSI and Ansys SIwave; EM sims using Ansys HFSS, SI-Wave, Cadence Clarity, and the ability to correlate that with real world challenges is a required skill.\nGood understanding of interposer, substrate, package, PCB level design rules, ability to perform routing feasibility studies using Cadence APD or PCB editor. Good understanding of chip-package interactions and failure mechanism at component and board level, thermal and warpage management.\nAbility to manage programs involving cross-functional teams. Strong interpersonal skills and willingness to learn new things are necessary along with the ability to work with stakeholders in multiple time zones across the globe. Ability to influence vendors to align their roadmap with company goals. Strong communication, presentation and documentation skills\nThe ideal candidate would have:\nPrior experience in data center AI accelerators, networking silicon, or custom HPC silicon. Board, system and rack level integration, thermal, mechanical, signal and power analysis.\nAbility to influence senior stakeholders across architecture, silicon design, system platform engineering, and supply chain\nExperience setting roadmaps, not just executing them.\nExperience with silicon disaggregation and reaggregation and memory integration.\nDemonstrated leadership driving cross-company supplier programs.\nExperience with VNA and TDR measurements for package and PCB characterization\nExperience in advanced package and substrate technologies with understanding of process and materials, component and board level reliability, warpage and thermal management.\nExpected Base Pay Range (USD)\n170,800 - 252,750, $ per annum\nThe successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.\nAdditional Compensation and Benefit Elements\nMarvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.\nAny applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at\nTAOps@marvell.com\n.\nInterview Integrity\nTo support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.\nThese tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.\nThis position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.\n#LI-MM1","company":"Marvelltechnology1","rawCompany":"marvelltechnology1","city":"Austin","state":"TX","isRemote":false,"isActive":false,"createdAt":"2026-04-14T10:41:33.143Z","occupations":[{"code":"17-2061.00","title":"Computer Hardware Engineers","slug":"computer-hardware-engineers"},{"code":"17-2072.00","title":"Electronics Engineers, Except Computer","slug":"electronics-engineers-except-computer"},{"code":"17-2071.00","title":"Electrical Engineers","slug":"electrical-engineers"}],"industries":[{"code":"334413","title":"Semiconductor and Related Device Manufacturing","slug":"semiconductor-and-related-device-manufacturing"},{"code":"541715","title":"Research and Development in the Physical, Engineering, and Life Sciences (except Nanotechnology and Biotechnology)","slug":"research-and-development-in-the-physical-engineering-and-life-sciences-except-nanotechnology-and-biotechnology"},{"code":"333242","title":"Semiconductor Machinery Manufacturing","slug":"semiconductor-machinery-manufacturing"}],"jobPosting":{"@context":"https://schema.org","@type":"JobPosting","title":"Advanced Packaging Technology Pathfinding and Development Engineer","description":"About Marvell\nMarvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.\nAt Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.\nYour Team, Your Impact\nThe Marvell Advanced Packaging R&D team is responsible for package design and technology development to meet the electrical, mechanical, thermal and system requirements for the next generation high performance computing (HPC), Artificial Intelligence (AI) and networking solutions. The group focuses on signal integrity, power integrity, thermal integrity, mechanical integrity, processability, manufacturability, and reliability, involving high speed signaling and complex power delivery networks (PDNs) requiring innovative and custom solutions to meet constantly evolving customer needs. Many of the new designs require multi-chip, multiple component configurations involving, but not limited to, 2.5D and 3D packages, Co-packaged copper or optics and advanced substrates. Marvell has partnered with the world's leading manufacturers to solve our customer’s most challenging designs and integrations with industry-leading packaging technologies.\nWhat You Can Expect\nDevelop packaging technology roadmap for AI XPU, XPU-attach and Switch\nExplore technologies beyond what is currently available, make recommendations, and create and protect IP to maximize performance. Create new package technology concepts from open ended ideas, perform routing feasibility, signal and power integrity studies for design optimization. Explore technology feasibility and create proof-of-concept samples and productize technologies.\nDefine package architecture including chiplet topology, interposer/substrate scaling, power delivery network strategy, and thermal design envelope. Lead co-design efforts across silicon design, floorplanning, PDN modeling, and mechanical/thermal reliability. Lead package material selection, substrate stack-up definition, mechanical modeling, and reliability analysis. Partner with silicon design teams to co-optimize die floorplan, bump map, TSV, and RDL requirements.\nWork with OSATs / Foundry partners to evaluate process capability, manufacturability, yield, and cost. Drive package qualification and reliability validation to volume readiness.\nWhat We're Looking For\nExperience in advanced package and substrate technologies with deep understanding of process and materials, component and board level reliability, warpage and thermal management. Experience in managing substrate and assembly material vendors, substrate manufacturers, OSATs and foundries.\nDeep knowledge of Electrical Engineering concepts, circuit extractions and simulation, as well as design methodology and strategies. Experience in signal and power integrity simulations, analysis and optimization for 2.5D and 3D packages including interface with memory, interposer, substrates and PCBs. Ability to determine optimal signal routing, power delivery verification and package size determination\nBachelor’s degree in mechanical engineering, material science or related fields and 15+ years of related professional experience or master’s degree and 12+ years of related professional experience or PhD degree / post-doc with 8+ years of experience.\nExperience interfacing with product design teams for optimized floor-planning, package related design input and power delivery network design.\nBachelor's degree in electrical engineering or related fields and 15+ years of related professional experience in signal and power integrity, or master’s degree and 10+ years of related professional experience, or PhD degree with 8+ years of experience.\nSkills needed to be successful in this role:\nAbility to develop an idea into a proof of concept and then a proof of concept into a productizable technology\nDeep understanding of fundamental concepts of signal and power integrity, transmission line and electromigration, and the ability to apply those concepts to create new design rules and explore new technologies utilizing current baseline for 2.5D/3D package technology including (a) CoWoS-S/R/L, (b) EMIB-T, (c) CPO, (d) CPC.\nMastery in tools and workflows to guide and enable the team on what sims need to be run: previous hands-on experience with signal and power integrity analyses using Cadence Sigrity PowerSI and Ansys SIwave; EM sims using Ansys HFSS, SI-Wave, Cadence Clarity, and the ability to correlate that with real world challenges is a required skill.\nGood understanding of interposer, substrate, package, PCB level design rules, ability to perform routing feasibility studies using Cadence APD or PCB editor. Good understanding of chip-package interactions and failure mechanism at component and board level, thermal and warpage management.\nAbility to manage programs involving cross-functional teams. Strong interpersonal skills and willingness to learn new things are necessary along with the ability to work with stakeholders in multiple time zones across the globe. Ability to influence vendors to align their roadmap with company goals. Strong communication, presentation and documentation skills\nThe ideal candidate would have:\nPrior experience in data center AI accelerators, networking silicon, or custom HPC silicon. Board, system and rack level integration, thermal, mechanical, signal and power analysis.\nAbility to influence senior stakeholders across architecture, silicon design, system platform engineering, and supply chain\nExperience setting roadmaps, not just executing them.\nExperience with silicon disaggregation and reaggregation and memory integration.\nDemonstrated leadership driving cross-company supplier programs.\nExperience with VNA and TDR measurements for package and PCB characterization\nExperience in advanced package and substrate technologies with understanding of process and materials, component and board level reliability, warpage and thermal management.\nExpected Base Pay Range (USD)\n170,800 - 252,750, $ per annum\nThe successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.\nAdditional Compensation and Benefit Elements\nMarvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.\nAny applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at\nTAOps@marvell.com\n.\nInterview Integrity\nTo support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.\nThese tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.\nThis position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.\n#LI-MM1","datePosted":"2026-04-14T10:41:33.143Z","dateModified":"2026-04-14T10:41:33.143Z","hiringOrganization":{"@type":"Organization","name":"Marvelltechnology1","sameAs":"https://jobsearcher.com"},"jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Austin","addressRegion":"TX","addressCountry":"US"}},"identifier":{"@type":"PropertyValue","name":"JobSearcher","value":"5c88f4f802060b4e05a45760"},"url":"https://jobsearcher.com/jobs/5c88f4f802060b4e05a45760"}}