{"schemaVersion":"jobsearcher.job.v1","id":"57cf17b9a38307f0eff2630d","url":"https://jobsearcher.com/jobs/57cf17b9a38307f0eff2630d","canonicalUrl":"https://jobsearcher.com/jobs/57cf17b9a38307f0eff2630d","title":"GPU Performance Software Development Engineer","description":"Overview:\nWHAT YOU DO AT AMD CHANGES EVERYTHING\nAt AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.\nResponsibilities:\nMission\nWave is a high-performance GPU programming language and compiler built for modern machine-learning workloads. It combines a Python-embedded DSL with an MLIR-based compiler stack to let engineers write kernels that are both expressive and fast.\n\nYour mission will be to own the end-to-end performance of Wave’s GPU kernels. You will design, implement, and continuously optimize hand-tuned kernels (GEMM, Attention, MoE, decoding) while shaping compiler and MLIR infrastructure to extract peak performance on modern accelerators. You will take responsibility for kernel performance, diagnose bottlenecks down to the instruction and scheduling level, and work across kernel code, compiler passes, and hardware models to close performance gaps against vendor libraries.\n\nCore Responsibilities\n\nOwn kernel performance for Wave\nOptimize critical kernels (GEMM, Attention, MoE, decoding) to be competitive with or exceed vendor libraries.\nProfile, analyze, and eliminate bottlenecks across memory, registers, instruction scheduling, and wave/warp execution.\nLow-level GPU optimization\nWrite and tune kernels using HIP / CUDA / inline assembly / intrinsics (e.g., MFMA / MMA).\nOptimize LDS/shared memory usage, register allocation, instruction scheduling, occupancy, and wave/warp utilization.\nReason about hardware details such as waves/warps, WGP/SM behavior, pipelines, cache hierarchies, and memory systems.\nCompiler & MLIR integration\nExtend and optimize MLIR dialects and lowering pipelines relevant to GPU code generation.\nBridge high-level representations (FX / Python DSL) to low-level MLIR and ISA-aware transformations.\nImplement compiler passes for tiling, vectorization, prefetching, pipelining, and layout transformations.\nPerformance modeling & tooling\nBuild mental and empirical performance models to guide kernel design.\nUse profiling tools (e.g., rocprof, Nsight, custom counters) and disassembly to validate hypotheses.\nCreate internal benchmarks, microkernels, and performance regression tests.\nArchitecture bring-up\nLead kernel and compiler optimization for new GPU architectures.\nAdapt kernels and compiler strategies to evolving hardware capabilities.\n\nRequired Qualifications\n\nDeep GPU performance expertise\nProven experience optimizing GPU kernels at the instruction and memory-system level.\nStrong understanding of GPU execution models (waves/warps, occupancy, latency hiding).\nLow-level programming\nProficiency in C++ and GPU programming (HIP or CUDA).\nExperience with GPU intrinsics, inline PTX / GCN assembly, or equivalent low-level code.\nCompiler experience\nHands-on experience with compilers, preferably MLIR.\nFamiliarity with compiler IRs, lowering pipelines, and performance-critical transformations.\nPerformance analysis\nAbility to read disassembly, analyze performance counters, and reason from first principles.\nTrack record of closing performance gaps against strong baselines.\nMasters in Computer Science or related field\n\nStrongly Preferred\n\nExperience with AMD GPUs (ROCm, CDNA, MI-series) or NVIDIA GPUs (Ampere/Hopper/Blackwell).\nExperience designing or maintaining a DSL, compiler backend, or GPU codegen pipeline.\nBackground in linear algebra kernels, attention mechanisms, or ML workloads.\nComfort working across Python frontends, MLIR, and backend codegen.\nPhD in Computer Science or related field\n\n#LI-G11\n\n#LI-HYBRID\n\nQualifications:\nBenefits offered are described: AMD benefits at a glance.\n\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\n\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.","company":"Advanced Micro Devices","rawCompany":"advanced micro devices","city":"San Jose","state":"CA","isRemote":false,"isActive":false,"createdAt":"2026-04-14T10:49:02.703Z","occupations":[{"code":"15-1252.00","title":"Software Developers","slug":"software-developers"},{"code":"17-2061.00","title":"Computer Hardware Engineers","slug":"computer-hardware-engineers"},{"code":"15-1299.08","title":"Computer Systems Engineers/Architects","slug":"computer-systems-engineers-architects"}],"industries":[{"code":"513210","title":"Software Publishers","slug":"software-publishers"},{"code":"541511","title":"Custom Computer Programming Services","slug":"custom-computer-programming-services"},{"code":"334111","title":"Electronic Computer Manufacturing","slug":"electronic-computer-manufacturing"}],"jobPosting":{"@context":"https://schema.org","@type":"JobPosting","title":"GPU Performance Software Development Engineer","description":"Overview:\nWHAT YOU DO AT AMD CHANGES EVERYTHING\nAt AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.\nResponsibilities:\nMission\nWave is a high-performance GPU programming language and compiler built for modern machine-learning workloads. It combines a Python-embedded DSL with an MLIR-based compiler stack to let engineers write kernels that are both expressive and fast.\n\nYour mission will be to own the end-to-end performance of Wave’s GPU kernels. You will design, implement, and continuously optimize hand-tuned kernels (GEMM, Attention, MoE, decoding) while shaping compiler and MLIR infrastructure to extract peak performance on modern accelerators. You will take responsibility for kernel performance, diagnose bottlenecks down to the instruction and scheduling level, and work across kernel code, compiler passes, and hardware models to close performance gaps against vendor libraries.\n\nCore Responsibilities\n\nOwn kernel performance for Wave\nOptimize critical kernels (GEMM, Attention, MoE, decoding) to be competitive with or exceed vendor libraries.\nProfile, analyze, and eliminate bottlenecks across memory, registers, instruction scheduling, and wave/warp execution.\nLow-level GPU optimization\nWrite and tune kernels using HIP / CUDA / inline assembly / intrinsics (e.g., MFMA / MMA).\nOptimize LDS/shared memory usage, register allocation, instruction scheduling, occupancy, and wave/warp utilization.\nReason about hardware details such as waves/warps, WGP/SM behavior, pipelines, cache hierarchies, and memory systems.\nCompiler & MLIR integration\nExtend and optimize MLIR dialects and lowering pipelines relevant to GPU code generation.\nBridge high-level representations (FX / Python DSL) to low-level MLIR and ISA-aware transformations.\nImplement compiler passes for tiling, vectorization, prefetching, pipelining, and layout transformations.\nPerformance modeling & tooling\nBuild mental and empirical performance models to guide kernel design.\nUse profiling tools (e.g., rocprof, Nsight, custom counters) and disassembly to validate hypotheses.\nCreate internal benchmarks, microkernels, and performance regression tests.\nArchitecture bring-up\nLead kernel and compiler optimization for new GPU architectures.\nAdapt kernels and compiler strategies to evolving hardware capabilities.\n\nRequired Qualifications\n\nDeep GPU performance expertise\nProven experience optimizing GPU kernels at the instruction and memory-system level.\nStrong understanding of GPU execution models (waves/warps, occupancy, latency hiding).\nLow-level programming\nProficiency in C++ and GPU programming (HIP or CUDA).\nExperience with GPU intrinsics, inline PTX / GCN assembly, or equivalent low-level code.\nCompiler experience\nHands-on experience with compilers, preferably MLIR.\nFamiliarity with compiler IRs, lowering pipelines, and performance-critical transformations.\nPerformance analysis\nAbility to read disassembly, analyze performance counters, and reason from first principles.\nTrack record of closing performance gaps against strong baselines.\nMasters in Computer Science or related field\n\nStrongly Preferred\n\nExperience with AMD GPUs (ROCm, CDNA, MI-series) or NVIDIA GPUs (Ampere/Hopper/Blackwell).\nExperience designing or maintaining a DSL, compiler backend, or GPU codegen pipeline.\nBackground in linear algebra kernels, attention mechanisms, or ML workloads.\nComfort working across Python frontends, MLIR, and backend codegen.\nPhD in Computer Science or related field\n\n#LI-G11\n\n#LI-HYBRID\n\nQualifications:\nBenefits offered are described: AMD benefits at a glance.\n\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\n\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.","datePosted":"2026-04-14T10:49:02.703Z","dateModified":"2026-04-14T10:49:02.703Z","hiringOrganization":{"@type":"Organization","name":"Advanced Micro Devices","sameAs":"https://jobsearcher.com"},"jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"San Jose","addressRegion":"CA","addressCountry":"US"}},"identifier":{"@type":"PropertyValue","name":"JobSearcher","value":"57cf17b9a38307f0eff2630d"},"url":"https://jobsearcher.com/jobs/57cf17b9a38307f0eff2630d"}}