{"schemaVersion":"jobsearcher.job.v1","id":"53e50eb39f8da7ebec7ca64d","url":"https://jobsearcher.com/jobs/53e50eb39f8da7ebec7ca64d","canonicalUrl":"https://jobsearcher.com/jobs/53e50eb39f8da7ebec7ca64d","title":"Senior ASIC Implementation Engineer - UPF, Timing Lead","description":"Amazon Kuiper Manufacturing Enterprises LLC in Sunnyvale is seeking an experienced ASIC implementation engineer to shape power-aware chip design for LEO satellite communications. You will collaborate with ASIC teams to define UPF-based power intents and drive RTL and netlist validation. You will establish flow for both logic and physical synthesis across multiple CMOS nodes, lead timing sign-off, coordinate with RFIC and P&R teams, and ensure DFM criteria are met through IR/EM checks.\n#J-18808-Ljbffr","company":"Amazon","rawCompany":"amazon","city":"Eastern","state":"KY","isRemote":false,"isActive":false,"createdAt":"2026-10-14T03:52:54.582Z","occupations":[{"code":"17-2072.00","title":"Electronics Engineers, Except Computer","slug":"electronics-engineers-except-computer"},{"code":"17-2061.00","title":"Computer Hardware Engineers","slug":"computer-hardware-engineers"},{"code":"17-2071.00","title":"Electrical Engineers","slug":"electrical-engineers"}],"industries":[{"code":"334413","title":"Semiconductor and Related Device Manufacturing","slug":"semiconductor-and-related-device-manufacturing"},{"code":"334419","title":"Other Electronic Component Manufacturing","slug":"other-electronic-component-manufacturing"},{"code":"334418","title":"Printed Circuit Assembly (Electronic Assembly) Manufacturing","slug":"printed-circuit-assembly-electronic-assembly-manufacturing"}],"jobPosting":{"@context":"https://schema.org","@type":"JobPosting","title":"Senior ASIC Implementation Engineer - UPF, Timing Lead","description":"Amazon Kuiper Manufacturing Enterprises LLC in Sunnyvale is seeking an experienced ASIC implementation engineer to shape power-aware chip design for LEO satellite communications. You will collaborate with ASIC teams to define UPF-based power intents and drive RTL and netlist validation. You will establish flow for both logic and physical synthesis across multiple CMOS nodes, lead timing sign-off, coordinate with RFIC and P&R teams, and ensure DFM criteria are met through IR/EM checks.\n#J-18808-Ljbffr","datePosted":"2026-10-14T03:52:54.582Z","dateModified":"2026-10-14T03:52:54.582Z","hiringOrganization":{"@type":"Organization","name":"Amazon","sameAs":"https://jobsearcher.com"},"jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Eastern","addressRegion":"KY","addressCountry":"US"}},"identifier":{"@type":"PropertyValue","name":"JobSearcher","value":"53e50eb39f8da7ebec7ca64d"},"url":"https://jobsearcher.com/jobs/53e50eb39f8da7ebec7ca64d"}}