{"schemaVersion":"jobsearcher.job.v1","id":"45c3509b44982f00bd2f61b8","url":"https://jobsearcher.com/jobs/45c3509b44982f00bd2f61b8","canonicalUrl":"https://jobsearcher.com/jobs/45c3509b44982f00bd2f61b8","title":"R&D Engineer Hardware 4","description":"Job Description\nDesign and develop verification and evaluation boards to test semiconductor IC products. Evaluate design goals and implement into hardware; design conception, package pin‑out feasibility studies, part selection, manufacturer and PCB material selection, PCB stack‑up, and schematic capture. Will have responsibility to design the PCB layout or oversee layout designers, simulation, board fabrication and assembly.\n\nResponsibilities\n\nPart identification and interconnects\n\nSignal integrity\n\nMechanical knowledge for typical board outline requirements\n\nMechanical stability and general brackets or fixtures\n\nCoordinate designs between analog chip designers, digital chip designers, package engineers, device verification test (DVT) engineers and product line managers\n\nCandidate must be an excellent communicator, both written and verbally. Able to host design reviews and attend various meetings that define design goals.\n\nAble to create design documentation, basic board operation summaries, bring up and debug, respond to questions about board use, and understand board limitations.\n\nDesired Experience and Capabilities\n\nHigh speed signal trace design\n\nMentor DxDesigner, Cadence Allegro use\n\nSignal integrity using 3D tools such as HFSS\n\nFPGA Verilog coding a plus\n\nMust be able to work independently\n\nSelf‑starter\n\nExperience: MSEE or equivalent degree. 6+ years of related experience\n\nCompensation And Benefits\nThe annual base salary range for this position is $108,000 - $172,800. This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.\n\nBroadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.\n\n#J-18808-Ljbffr","company":"SupportFinity","rawCompany":"supportfinity","city":"California","state":"MO","isRemote":false,"isActive":false,"createdAt":"2026-06-20T04:26:47.393Z","occupations":[{"code":"17-2061.00","title":"Computer Hardware Engineers","slug":"computer-hardware-engineers"},{"code":"17-2072.00","title":"Electronics Engineers, Except Computer","slug":"electronics-engineers-except-computer"},{"code":"17-2199.00","title":"Engineers, All Other","slug":"engineers-all-other"}],"industries":[{"code":"334418","title":"Printed Circuit Assembly (Electronic Assembly) Manufacturing","slug":"printed-circuit-assembly-electronic-assembly-manufacturing"},{"code":"334419","title":"Other Electronic Component Manufacturing","slug":"other-electronic-component-manufacturing"},{"code":"334413","title":"Semiconductor and Related Device Manufacturing","slug":"semiconductor-and-related-device-manufacturing"}],"jobPosting":{"@context":"https://schema.org","@type":"JobPosting","title":"R&D Engineer Hardware 4","description":"Job Description\nDesign and develop verification and evaluation boards to test semiconductor IC products. Evaluate design goals and implement into hardware; design conception, package pin‑out feasibility studies, part selection, manufacturer and PCB material selection, PCB stack‑up, and schematic capture. Will have responsibility to design the PCB layout or oversee layout designers, simulation, board fabrication and assembly.\n\nResponsibilities\n\nPart identification and interconnects\n\nSignal integrity\n\nMechanical knowledge for typical board outline requirements\n\nMechanical stability and general brackets or fixtures\n\nCoordinate designs between analog chip designers, digital chip designers, package engineers, device verification test (DVT) engineers and product line managers\n\nCandidate must be an excellent communicator, both written and verbally. Able to host design reviews and attend various meetings that define design goals.\n\nAble to create design documentation, basic board operation summaries, bring up and debug, respond to questions about board use, and understand board limitations.\n\nDesired Experience and Capabilities\n\nHigh speed signal trace design\n\nMentor DxDesigner, Cadence Allegro use\n\nSignal integrity using 3D tools such as HFSS\n\nFPGA Verilog coding a plus\n\nMust be able to work independently\n\nSelf‑starter\n\nExperience: MSEE or equivalent degree. 6+ years of related experience\n\nCompensation And Benefits\nThe annual base salary range for this position is $108,000 - $172,800. This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.\n\nBroadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.\n\n#J-18808-Ljbffr","datePosted":"2026-06-20T04:26:47.393Z","dateModified":"2026-06-20T04:26:47.393Z","hiringOrganization":{"@type":"Organization","name":"SupportFinity","sameAs":"https://jobsearcher.com"},"jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"California","addressRegion":"MO","addressCountry":"US"}},"identifier":{"@type":"PropertyValue","name":"JobSearcher","value":"45c3509b44982f00bd2f61b8"},"url":"https://jobsearcher.com/jobs/45c3509b44982f00bd2f61b8"}}