{"schemaVersion":"jobsearcher.job.v1","id":"3f26ed02cf45b24fc55bd916","url":"https://jobsearcher.com/jobs/3f26ed02cf45b24fc55bd916","canonicalUrl":"https://jobsearcher.com/jobs/3f26ed02cf45b24fc55bd916","title":"DFT Engineer","description":"Benefits:\nDay-1 Onsite\nCompetitive salary\nOpportunity for advancement\nDFT Engineer (Design for Test)\nLocation: Santa Clara, CA (Onsite)\nEmployment Type: Long-Term Contract\nInterview Process: Virtual Interviews\nCompensation: Based on Experience (DOE)\nEngagement: ANY\nPreference: Local candidates or those able to work onsite.\n\nWe are seeking an experienced DFT Engineer to join a high-performing ASIC/SoC engineering team.\nIn this role, you will be responsible for designing and implementing Design-for-Test (DFT) solutions that ensure high manufacturing quality, test coverage, and efficient production testing for complex semiconductor devices.\n\nKey Responsibilities\nDesign and implement DFT architecture for ASIC and SoC designs.\nDevelop and integrate Scan Compression, MBIST, LBIST, JTAG, and IJTAG solutions.\nPerform ATPG, fault simulation, and test coverage analysis.\nSupport silicon bring-up, debug, characterization, and production test activities.\nCollaborate closely with Design, Verification, Physical Design, and Product Engineering teams throughout the development lifecycle.\nRequired Qualifications\n5+ years of hands-on experience in Design for Test (DFT).\nStrong expertise in Scan, Scan Compression, MBIST, LBIST, ATPG, and JTAG technologies.\nSolid understanding of IEEE 1149.1, IEEE 1500, and IEEE 1687 (IJTAG) standards.\nExperience with one or more industry-standard DFT tools:\nSynopsys TestMAX / DFT Compiler\nSiemens Tessent\nCadence Modus\nProficiency in Verilog and/or SystemVerilog.\nScripting experience using Python, Perl, Tcl, or Shell.\nPreferred Qualifications\nExperience with ASIC/SoC development.\nBackground in silicon bring-up, debug, and production test.\nStrong problem-solving skills and the ability to work effectively in cross-functional engineering teams.\nIf you’re passionate about developing robust DFT solutions for advanced semiconductor products, we’d love to hear from you.","company":"Select Minds","rawCompany":"select minds","city":"Santa Clara","state":"CA","isRemote":false,"isActive":false,"createdAt":"2026-08-04T19:14:18.923Z","occupations":[{"code":"17-2072.00","title":"Electronics Engineers, Except Computer","slug":"electronics-engineers-except-computer"},{"code":"17-2199.00","title":"Engineers, All Other","slug":"engineers-all-other"},{"code":"17-2061.00","title":"Computer Hardware Engineers","slug":"computer-hardware-engineers"}],"industries":[{"code":"334413","title":"Semiconductor and Related Device Manufacturing","slug":"semiconductor-and-related-device-manufacturing"},{"code":"541512","title":"Computer Systems Design Services","slug":"computer-systems-design-services"},{"code":"334419","title":"Other Electronic Component Manufacturing","slug":"other-electronic-component-manufacturing"}],"jobPosting":{"@context":"https://schema.org","@type":"JobPosting","title":"DFT Engineer","description":"Benefits:\nDay-1 Onsite\nCompetitive salary\nOpportunity for advancement\nDFT Engineer (Design for Test)\nLocation: Santa Clara, CA (Onsite)\nEmployment Type: Long-Term Contract\nInterview Process: Virtual Interviews\nCompensation: Based on Experience (DOE)\nEngagement: ANY\nPreference: Local candidates or those able to work onsite.\n\nWe are seeking an experienced DFT Engineer to join a high-performing ASIC/SoC engineering team.\nIn this role, you will be responsible for designing and implementing Design-for-Test (DFT) solutions that ensure high manufacturing quality, test coverage, and efficient production testing for complex semiconductor devices.\n\nKey Responsibilities\nDesign and implement DFT architecture for ASIC and SoC designs.\nDevelop and integrate Scan Compression, MBIST, LBIST, JTAG, and IJTAG solutions.\nPerform ATPG, fault simulation, and test coverage analysis.\nSupport silicon bring-up, debug, characterization, and production test activities.\nCollaborate closely with Design, Verification, Physical Design, and Product Engineering teams throughout the development lifecycle.\nRequired Qualifications\n5+ years of hands-on experience in Design for Test (DFT).\nStrong expertise in Scan, Scan Compression, MBIST, LBIST, ATPG, and JTAG technologies.\nSolid understanding of IEEE 1149.1, IEEE 1500, and IEEE 1687 (IJTAG) standards.\nExperience with one or more industry-standard DFT tools:\nSynopsys TestMAX / DFT Compiler\nSiemens Tessent\nCadence Modus\nProficiency in Verilog and/or SystemVerilog.\nScripting experience using Python, Perl, Tcl, or Shell.\nPreferred Qualifications\nExperience with ASIC/SoC development.\nBackground in silicon bring-up, debug, and production test.\nStrong problem-solving skills and the ability to work effectively in cross-functional engineering teams.\nIf you’re passionate about developing robust DFT solutions for advanced semiconductor products, we’d love to hear from you.","datePosted":"2026-08-04T19:14:18.923Z","dateModified":"2026-08-04T19:14:18.923Z","hiringOrganization":{"@type":"Organization","name":"Select Minds","sameAs":"https://jobsearcher.com"},"jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Santa Clara","addressRegion":"CA","addressCountry":"US"}},"identifier":{"@type":"PropertyValue","name":"JobSearcher","value":"3f26ed02cf45b24fc55bd916"},"url":"https://jobsearcher.com/jobs/3f26ed02cf45b24fc55bd916"}}