{"schemaVersion":"jobsearcher.job.v1","id":"3efb560994a24eda52b24320","url":"https://jobsearcher.com/jobs/3efb560994a24eda52b24320","canonicalUrl":"https://jobsearcher.com/jobs/3efb560994a24eda52b24320","title":"Test Engineer","description":"Efficient is developing the world's most energy-efficient general-purpose computer processor. Efficient's patented technology uses 100x less energy than state of the art commercially available ultra-low-power processors and is programmable using standard high-level programming languages and AI/ML frameworks. This level of efficiency makes perpetual, pervasive intelligence possible: run AI/ML continuously on a AA battery for 5-10 years. Our platform's unprecedented level of efficiency enables IoT devices to intelligently capture and curate first-party data to drive the next major computing revolution\nEfficient Computer is a fabless semiconductor startup headquartered in Pittsburgh, PA, building energy-efficient processors for edge compute, embedded AI, and high-performance applications. Our team designs, tapes out, and brings up custom silicon across multiple process nodes, working closely with world-class foundry and OSAT partners to deliver differentiated chips from concept to production. Efficient Computer is looking for a Test Engineer with hands-on DFT and fabless semiconductor test experience to join our Operations team. This is a mid-level role sitting at the intersection of Hardware Engineering and Supply Chain and Operations.\n\nThe right candidate has worked across the full test lifecycle - from DFT strategy and ATPG pattern generation through ATE bringup, OSAT coordination, and production test - and is equally comfortable working with external suppliers as they are with internal hardware engineers. You will serve as the primary interface between our engineering team and our foundry, OSAT, and test partners, owning test engineering across our active chip programs and scaling that foundation to future products.\n\nWhat You Will Do\nDFT Strategy and Pattern Development\nPartner with external design partners and internal hardware engineers to define and execute DFT strategy for each chip program\nGenerate, validate, and deliver ATPG patterns including scan, MBIST, JTAG, and embedded memory read and write sequences\nDevelop and maintain STIL and PDL test program files for ATE execution\nDrive DFT sign-off deliverables and resolve pattern-level issues in coordination with external partners\nSupport setup pattern generation including power-up and power-down sequences, DFT entry sequences, and test mode initialization\nUnderstand and define power rail sequencing requirements for ATE execution to ensure safe device bringup\nATE Bringup and Test Program Development\nDevelop and debug test programs on ATE platforms including Advantest and Teradyne systems\nExecute first silicon bringup on new tapeouts in partnership with hardware engineers and OSAT test teams\nCharacterize device behavior across voltage, temperature, and frequency corners\nSupport load board bring-up and interface hardware validation\nDefine and manage test flows including wafer probe, final test, and bin sort\nUnderstand test time optimization strategies such as pattern flow sequencing to minimize unnecessary power cycles\nOSAT and Supplier Coordination\nServe as the primary test engineering interface with OSAT partners and test houses\nManage test program handoff to OSAT including documentation, qualification, and acceptance criteria\nCoordinate pattern delivery between design partners and OSAT to ensure format compatibility across STIL and SVF as required\nTrack and analyze yield data from probe and final test, escalate anomalies, and drive corrective actions\nSupport die traceability and OTP programming flows in production bin sort\nCoordinate with supply chain and operations on test capacity planning and lot scheduling\nCross-Program Ownership\nOwn test engineering across multiple active chip programs simultaneously\nBuild scalable test infrastructure and documentation that carries forward to future programs\nContribute to DFT reviews, tapeout checklists, and test escape analysis\nHelp define and mature internal test engineering capabilities over time\nWhat You Bring\nRequired\n5+ years of semiconductor test engineering experience in a fabless or IDM environment\nHands-on DFT experience including scan insertion, ATPG, MBIST, and JTAG boundary scan\nExperience generating and validating STIL patterns and working with test pattern delivery packages\nATE test program development experience on Advantest or Teradyne platforms\nExperience supporting wafer probe and final test at an OSAT or test house, including load board bringup\nFamiliarity with power sequencing requirements and DFT entry flows for ATE test program development\nAbility to work directly with external design partners and OSAT suppliers to coordinate pattern delivery and test execution\nStrong written and verbal communication skills - this role requires ongoing collaboration with external partners across multiple time zones\nPreferred\nExperience with embedded memory test including characterization and programming of non-volatile memory technologies\nExposure to high-speed serial interface test such as memory interfaces or camera and display interconnect protocols\nFamiliarity with DFT tools from major EDA vendors\nExperience at a fabless startup or small team where test engineering scope is broad\nExposure to leading-edge process nodes at 28nm or below\nExperience with ATE yield analysis and test time optimization\nScripting ability in Python or Perl for data analysis and test automation\nExperience generating VCD from RTL simulation and porting to STIL format\nWe offer a competitive salary for this role, generally ranging from $150,000 to $190,000, along with meaningful equity and comprehensive benefits. The final compensation package will be based on your experience and location, with some flexibility to ensure we align with the right candidate.\nWhy Join Efficient?\nEfficient offers a competitive compensation and benefits package, including 401K match, company-paid benefits, equity program, paid parental leave, and flexibility. We are committed to personal and professional development and strive to grow together as people and as a company.","company":"Efficient Computer","rawCompany":"efficient computer","city":"Austin","state":"TX","isRemote":false,"isActive":false,"createdAt":"2026-08-07T10:40:01.515Z","occupations":[{"code":"17-2061.00","title":"Computer Hardware Engineers","slug":"computer-hardware-engineers"},{"code":"17-2112.02","title":"Validation Engineers","slug":"validation-engineers"},{"code":"17-2072.00","title":"Electronics Engineers, Except Computer","slug":"electronics-engineers-except-computer"}],"industries":[{"code":"334413","title":"Semiconductor and Related Device Manufacturing","slug":"semiconductor-and-related-device-manufacturing"},{"code":"334111","title":"Electronic Computer Manufacturing","slug":"electronic-computer-manufacturing"},{"code":"541715","title":"Research and Development in the Physical, Engineering, and Life Sciences (except Nanotechnology and Biotechnology)","slug":"research-and-development-in-the-physical-engineering-and-life-sciences-except-nanotechnology-and-biotechnology"}],"jobPosting":{"@context":"https://schema.org","@type":"JobPosting","title":"Test Engineer","description":"Efficient is developing the world's most energy-efficient general-purpose computer processor. Efficient's patented technology uses 100x less energy than state of the art commercially available ultra-low-power processors and is programmable using standard high-level programming languages and AI/ML frameworks. This level of efficiency makes perpetual, pervasive intelligence possible: run AI/ML continuously on a AA battery for 5-10 years. Our platform's unprecedented level of efficiency enables IoT devices to intelligently capture and curate first-party data to drive the next major computing revolution\nEfficient Computer is a fabless semiconductor startup headquartered in Pittsburgh, PA, building energy-efficient processors for edge compute, embedded AI, and high-performance applications. Our team designs, tapes out, and brings up custom silicon across multiple process nodes, working closely with world-class foundry and OSAT partners to deliver differentiated chips from concept to production. Efficient Computer is looking for a Test Engineer with hands-on DFT and fabless semiconductor test experience to join our Operations team. This is a mid-level role sitting at the intersection of Hardware Engineering and Supply Chain and Operations.\n\nThe right candidate has worked across the full test lifecycle - from DFT strategy and ATPG pattern generation through ATE bringup, OSAT coordination, and production test - and is equally comfortable working with external suppliers as they are with internal hardware engineers. You will serve as the primary interface between our engineering team and our foundry, OSAT, and test partners, owning test engineering across our active chip programs and scaling that foundation to future products.\n\nWhat You Will Do\nDFT Strategy and Pattern Development\nPartner with external design partners and internal hardware engineers to define and execute DFT strategy for each chip program\nGenerate, validate, and deliver ATPG patterns including scan, MBIST, JTAG, and embedded memory read and write sequences\nDevelop and maintain STIL and PDL test program files for ATE execution\nDrive DFT sign-off deliverables and resolve pattern-level issues in coordination with external partners\nSupport setup pattern generation including power-up and power-down sequences, DFT entry sequences, and test mode initialization\nUnderstand and define power rail sequencing requirements for ATE execution to ensure safe device bringup\nATE Bringup and Test Program Development\nDevelop and debug test programs on ATE platforms including Advantest and Teradyne systems\nExecute first silicon bringup on new tapeouts in partnership with hardware engineers and OSAT test teams\nCharacterize device behavior across voltage, temperature, and frequency corners\nSupport load board bring-up and interface hardware validation\nDefine and manage test flows including wafer probe, final test, and bin sort\nUnderstand test time optimization strategies such as pattern flow sequencing to minimize unnecessary power cycles\nOSAT and Supplier Coordination\nServe as the primary test engineering interface with OSAT partners and test houses\nManage test program handoff to OSAT including documentation, qualification, and acceptance criteria\nCoordinate pattern delivery between design partners and OSAT to ensure format compatibility across STIL and SVF as required\nTrack and analyze yield data from probe and final test, escalate anomalies, and drive corrective actions\nSupport die traceability and OTP programming flows in production bin sort\nCoordinate with supply chain and operations on test capacity planning and lot scheduling\nCross-Program Ownership\nOwn test engineering across multiple active chip programs simultaneously\nBuild scalable test infrastructure and documentation that carries forward to future programs\nContribute to DFT reviews, tapeout checklists, and test escape analysis\nHelp define and mature internal test engineering capabilities over time\nWhat You Bring\nRequired\n5+ years of semiconductor test engineering experience in a fabless or IDM environment\nHands-on DFT experience including scan insertion, ATPG, MBIST, and JTAG boundary scan\nExperience generating and validating STIL patterns and working with test pattern delivery packages\nATE test program development experience on Advantest or Teradyne platforms\nExperience supporting wafer probe and final test at an OSAT or test house, including load board bringup\nFamiliarity with power sequencing requirements and DFT entry flows for ATE test program development\nAbility to work directly with external design partners and OSAT suppliers to coordinate pattern delivery and test execution\nStrong written and verbal communication skills - this role requires ongoing collaboration with external partners across multiple time zones\nPreferred\nExperience with embedded memory test including characterization and programming of non-volatile memory technologies\nExposure to high-speed serial interface test such as memory interfaces or camera and display interconnect protocols\nFamiliarity with DFT tools from major EDA vendors\nExperience at a fabless startup or small team where test engineering scope is broad\nExposure to leading-edge process nodes at 28nm or below\nExperience with ATE yield analysis and test time optimization\nScripting ability in Python or Perl for data analysis and test automation\nExperience generating VCD from RTL simulation and porting to STIL format\nWe offer a competitive salary for this role, generally ranging from $150,000 to $190,000, along with meaningful equity and comprehensive benefits. The final compensation package will be based on your experience and location, with some flexibility to ensure we align with the right candidate.\nWhy Join Efficient?\nEfficient offers a competitive compensation and benefits package, including 401K match, company-paid benefits, equity program, paid parental leave, and flexibility. We are committed to personal and professional development and strive to grow together as people and as a company.","datePosted":"2026-08-07T10:40:01.515Z","dateModified":"2026-08-07T10:40:01.515Z","hiringOrganization":{"@type":"Organization","name":"Efficient Computer","sameAs":"https://jobsearcher.com"},"jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Austin","addressRegion":"TX","addressCountry":"US"}},"identifier":{"@type":"PropertyValue","name":"JobSearcher","value":"3efb560994a24eda52b24320"},"url":"https://jobsearcher.com/jobs/3efb560994a24eda52b24320"}}