{"schemaVersion":"jobsearcher.job.v1","id":"3b42471dc1e761fcd2decf25","url":"https://jobsearcher.com/jobs/3b42471dc1e761fcd2decf25","canonicalUrl":"https://jobsearcher.com/jobs/3b42471dc1e761fcd2decf25","title":"Design Verification Engineer","description":"More emphasis on the candidate who has worked on these protocols : PCIe, Ethernet, die-to-die / chip-to-chip, HBM, DDR.\n\n*Design Verification Engineer *\n\n*Location:* San Jose, CA & Austin, TX -\n\n*Please find the JD:*\n\n*Job Summary*\nWe are seeking a Design Verification Engineer to join our Interface IP DV team. You will work with architects, designers, and vendors to ensure that all our architecture requirements are met in the IP subsystems and interfaces being created, validate correctness and performance across the full hardware-software stack. This role demands creativity, deep technical ability, and the drive to tackle complex verification challenges.\n*Key responsibilities:*\nEnd to end ownership of one or more of the following *IP subsystems: PCIe, Ethernet, CPU (arc/arm), *low power peripherals, sensors\nUnderstand vendor IP configurations and handle handshake with internal IP team\nDevelop and maintain UVM/SystemVerilog-based verification environments to ensure functional correctness, performance, and compliance with IP specifications.\nCollaborate with integration and SoC DV teams to validate seamless interaction of external IPs within the broader chip architecture.\nDrive coverage closure and sign-off by defining metrics, analyzing gaps, and ensuring comprehensive verification across corner cases and stress scenarios.\n*You may be a good fit if you have*\n6 to 12 years of design verification experience\nYou enjoy digging deep into complex verification challenges and finding creative ways to expose corner-case bugs.\nYou have hands-on experience with industry-standard verification methodologies like SystemVerilog/UVM and understand how to build scalable, reusable testbenches.\nYou are comfortable working with standard IP interfaces and protocols such as PCIe, Ethernet, AXI/AMBA, or ARM/ARC CPUs.\nYou thrive in a fast-paced startup environment and can take ownership of projects with minimal direction.\nYou collaborate naturally with cross-functional teams — from RTL design to software and emulation — and can clearly communicate technical insights.\n*Strong candidates may also have experience with:*\nExperience handling vendors and integration of IP/VIP’s\nUVM/System Verilog\n\nPay: $120,000.00 - $140,000.00 per year\n\nWork Location: In person","company":"Sign In Solution","rawCompany":"sign in solution","city":"Austin","state":"TX","isRemote":false,"isActive":false,"createdAt":"2026-09-12T10:19:36.495Z","occupations":[{"code":"17-2112.02","title":"Validation Engineers","slug":"validation-engineers"},{"code":"17-2061.00","title":"Computer Hardware Engineers","slug":"computer-hardware-engineers"},{"code":"15-1299.08","title":"Computer Systems Engineers/Architects","slug":"computer-systems-engineers-architects"}],"industries":[{"code":"541512","title":"Computer Systems Design Services","slug":"computer-systems-design-services"},{"code":"334111","title":"Electronic Computer Manufacturing","slug":"electronic-computer-manufacturing"},{"code":"334413","title":"Semiconductor and Related Device Manufacturing","slug":"semiconductor-and-related-device-manufacturing"}],"jobPosting":{"@context":"https://schema.org","@type":"JobPosting","title":"Design Verification Engineer","description":"More emphasis on the candidate who has worked on these protocols : PCIe, Ethernet, die-to-die / chip-to-chip, HBM, DDR.\n\n*Design Verification Engineer *\n\n*Location:* San Jose, CA & Austin, TX -\n\n*Please find the JD:*\n\n*Job Summary*\nWe are seeking a Design Verification Engineer to join our Interface IP DV team. You will work with architects, designers, and vendors to ensure that all our architecture requirements are met in the IP subsystems and interfaces being created, validate correctness and performance across the full hardware-software stack. This role demands creativity, deep technical ability, and the drive to tackle complex verification challenges.\n*Key responsibilities:*\nEnd to end ownership of one or more of the following *IP subsystems: PCIe, Ethernet, CPU (arc/arm), *low power peripherals, sensors\nUnderstand vendor IP configurations and handle handshake with internal IP team\nDevelop and maintain UVM/SystemVerilog-based verification environments to ensure functional correctness, performance, and compliance with IP specifications.\nCollaborate with integration and SoC DV teams to validate seamless interaction of external IPs within the broader chip architecture.\nDrive coverage closure and sign-off by defining metrics, analyzing gaps, and ensuring comprehensive verification across corner cases and stress scenarios.\n*You may be a good fit if you have*\n6 to 12 years of design verification experience\nYou enjoy digging deep into complex verification challenges and finding creative ways to expose corner-case bugs.\nYou have hands-on experience with industry-standard verification methodologies like SystemVerilog/UVM and understand how to build scalable, reusable testbenches.\nYou are comfortable working with standard IP interfaces and protocols such as PCIe, Ethernet, AXI/AMBA, or ARM/ARC CPUs.\nYou thrive in a fast-paced startup environment and can take ownership of projects with minimal direction.\nYou collaborate naturally with cross-functional teams — from RTL design to software and emulation — and can clearly communicate technical insights.\n*Strong candidates may also have experience with:*\nExperience handling vendors and integration of IP/VIP’s\nUVM/System Verilog\n\nPay: $120,000.00 - $140,000.00 per year\n\nWork Location: In person","datePosted":"2026-09-12T10:19:36.495Z","dateModified":"2026-09-12T10:19:36.495Z","hiringOrganization":{"@type":"Organization","name":"Sign In Solution","sameAs":"https://jobsearcher.com"},"jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Austin","addressRegion":"TX","addressCountry":"US"}},"identifier":{"@type":"PropertyValue","name":"JobSearcher","value":"3b42471dc1e761fcd2decf25"},"url":"https://jobsearcher.com/jobs/3b42471dc1e761fcd2decf25"}}