{"schemaVersion":"jobsearcher.job.v1","id":"37a38c84f9ef40aa41df4c98","url":"https://jobsearcher.com/jobs/37a38c84f9ef40aa41df4c98","canonicalUrl":"https://jobsearcher.com/jobs/37a38c84f9ef40aa41df4c98","title":"DFT Engineer - #","description":"$70-$75 per hour\n\nAustin, TX\n\nContract\n\nDuration: 12 months Contract\n\nJob Description\n\nWe are seeking an experienced Senior/Lead DFT Engineer to join our semiconductor design team. The ideal candidate will have strong expertise in Design for Test (DFT) methodologies, including Scan, ATPG, MBIST, JTAG, simulation, and Post‑Silicon Diagnosis at both block and SoC levels.\n\nThe candidate will play a key role in defining DFT architecture, implementing test solutions, improving test coverage, and supporting silicon bring‑up activities.\n\nExperience with Siemens Tessent (including Streaming Scan Network (SSN)/Streaming Scan Architecture) and Synopsys DFT tools is highly preferred.\n\nResponsibilities\n\nDefine, architect, and implement DFT solutions for complex ASIC/SoC designs.\n\nImplement and validate DFT structures at both block and SoC levels.\n\nGenerate and verify ATPG patterns to achieve target fault coverage and test quality.\n\nPerform gate‑level simulations (GLS) to validate DFT implementation and test patterns.\n\nDevelop DFT specifications, methodologies, and implementation flows for complex designs.\n\nAnalyze and debug DFT‑related issues including scan chain failures, ATPG violations, MBIST failures, low coverage issues, and silicon test failures.\n\nCollaborate closely with RTL, Synthesis, STA, Physical Design, and Verification teams to resolve DFT integration and timing challenges.\n\nWork with Product/Test Engineering teams during silicon bring‑up and production ramp‑up activities.\n\nSupport silicon debug activities by collecting, analyzing, and interpreting failure data to identify root causes and corrective actions.\n\nDrive DFT signoff activities including coverage analysis, pattern validation, and test readiness reviews.\n\nDevelop and maintain automation scripts and custom DFT flows using TCL and other scripting languages.\n\nExperience\n\n8–10+ years of hands‑on experience in Design for Test (DFT) for ASIC/SoC designs.\n\nJTAG/Boundary Scan\n\nCompression Techniques\n\nFault Coverage Analysis\n\nGate‑Level Simulations\n\nPost‑Silicon Debug and Diagnosis\n\nExperience implementing DFT solutions from architecture through silicon validation.\n\nStrong understanding of DFT methodologies, industry standards, and best practices.\n\nProven experience in debugging DFT issues across RTL, netlist, and silicon stages.\n\nHands‑on experience with Siemens Tessent tool suite for:\n\nScan Insertion\n\nATPG\n\nDiagnosis\n\nMBIST\n\nSSN (Streaming Scan Network) / SSM\n\nExperience with Synopsys DFT tools and associated implementation flows.\n\nStrong knowledge of synthesis, timing closure, and physical design impacts on DFT implementation.\n\nProficiency in TCL scripting for automation and flow development\n\nSkillset\n\nHands‑on experience with Streaming Scan Network (SSN) / Streaming Scan Architecture (SSA) in Siemens Tessent environments.\n\nExperience with large‑scale SoC and multi‑core architectures.\n\nKnowledge of advanced DFT techniques including:\n\nTest Compression\n\nHierarchical DFT\n\nDiagnosis‑driven Yield Analysis\n\nLow‑Power ATPG\n\nExperience supporting production test and yield improvement initiatives.\n\nFamiliarity with semiconductor manufacturing test flows and ATE environments.\n\nEducation\n\nBachelor's degree in engineering\n\nAdditional Qualifications\n\nLicenses: Not required\n\nCertifications: Not required\n\nShift Hours: 8:00AM -5:00 PM AST\n\nUS Tech Solutions is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, colour, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.\n\nBy applying, you acknowledge that AI‑assisted tools may be used during hiring.\n\n#J-18808-Ljbffr","company":"U.S. Tech Solutions","rawCompany":"us tech solutions","city":"Austin","state":"TX","isRemote":false,"isActive":true,"createdAt":"2026-06-22T03:21:14.822Z","occupations":[{"code":"17-2072.00","title":"Electronics Engineers, Except Computer","slug":"electronics-engineers-except-computer"},{"code":"17-2199.00","title":"Engineers, All Other","slug":"engineers-all-other"},{"code":"17-3023.00","title":"Electrical and Electronic Engineering Technologists and Technicians","slug":"electrical-and-electronic-engineering-technologists-and-technicians"}],"industries":[{"code":"334413","title":"Semiconductor and Related Device Manufacturing","slug":"semiconductor-and-related-device-manufacturing"},{"code":"541512","title":"Computer Systems Design Services","slug":"computer-systems-design-services"},{"code":"541330","title":"Engineering Services","slug":"engineering-services"}],"jobPosting":{"@context":"https://schema.org","@type":"JobPosting","title":"DFT Engineer - #","description":"$70-$75 per hour\n\nAustin, TX\n\nContract\n\nDuration: 12 months Contract\n\nJob Description\n\nWe are seeking an experienced Senior/Lead DFT Engineer to join our semiconductor design team. The ideal candidate will have strong expertise in Design for Test (DFT) methodologies, including Scan, ATPG, MBIST, JTAG, simulation, and Post‑Silicon Diagnosis at both block and SoC levels.\n\nThe candidate will play a key role in defining DFT architecture, implementing test solutions, improving test coverage, and supporting silicon bring‑up activities.\n\nExperience with Siemens Tessent (including Streaming Scan Network (SSN)/Streaming Scan Architecture) and Synopsys DFT tools is highly preferred.\n\nResponsibilities\n\nDefine, architect, and implement DFT solutions for complex ASIC/SoC designs.\n\nImplement and validate DFT structures at both block and SoC levels.\n\nGenerate and verify ATPG patterns to achieve target fault coverage and test quality.\n\nPerform gate‑level simulations (GLS) to validate DFT implementation and test patterns.\n\nDevelop DFT specifications, methodologies, and implementation flows for complex designs.\n\nAnalyze and debug DFT‑related issues including scan chain failures, ATPG violations, MBIST failures, low coverage issues, and silicon test failures.\n\nCollaborate closely with RTL, Synthesis, STA, Physical Design, and Verification teams to resolve DFT integration and timing challenges.\n\nWork with Product/Test Engineering teams during silicon bring‑up and production ramp‑up activities.\n\nSupport silicon debug activities by collecting, analyzing, and interpreting failure data to identify root causes and corrective actions.\n\nDrive DFT signoff activities including coverage analysis, pattern validation, and test readiness reviews.\n\nDevelop and maintain automation scripts and custom DFT flows using TCL and other scripting languages.\n\nExperience\n\n8–10+ years of hands‑on experience in Design for Test (DFT) for ASIC/SoC designs.\n\nJTAG/Boundary Scan\n\nCompression Techniques\n\nFault Coverage Analysis\n\nGate‑Level Simulations\n\nPost‑Silicon Debug and Diagnosis\n\nExperience implementing DFT solutions from architecture through silicon validation.\n\nStrong understanding of DFT methodologies, industry standards, and best practices.\n\nProven experience in debugging DFT issues across RTL, netlist, and silicon stages.\n\nHands‑on experience with Siemens Tessent tool suite for:\n\nScan Insertion\n\nATPG\n\nDiagnosis\n\nMBIST\n\nSSN (Streaming Scan Network) / SSM\n\nExperience with Synopsys DFT tools and associated implementation flows.\n\nStrong knowledge of synthesis, timing closure, and physical design impacts on DFT implementation.\n\nProficiency in TCL scripting for automation and flow development\n\nSkillset\n\nHands‑on experience with Streaming Scan Network (SSN) / Streaming Scan Architecture (SSA) in Siemens Tessent environments.\n\nExperience with large‑scale SoC and multi‑core architectures.\n\nKnowledge of advanced DFT techniques including:\n\nTest Compression\n\nHierarchical DFT\n\nDiagnosis‑driven Yield Analysis\n\nLow‑Power ATPG\n\nExperience supporting production test and yield improvement initiatives.\n\nFamiliarity with semiconductor manufacturing test flows and ATE environments.\n\nEducation\n\nBachelor's degree in engineering\n\nAdditional Qualifications\n\nLicenses: Not required\n\nCertifications: Not required\n\nShift Hours: 8:00AM -5:00 PM AST\n\nUS Tech Solutions is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, colour, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.\n\nBy applying, you acknowledge that AI‑assisted tools may be used during hiring.\n\n#J-18808-Ljbffr","datePosted":"2026-06-22T03:21:14.822Z","dateModified":"2026-06-22T03:21:14.822Z","hiringOrganization":{"@type":"Organization","name":"U.S. Tech Solutions","sameAs":"https://jobsearcher.com"},"jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Austin","addressRegion":"TX","addressCountry":"US"}},"identifier":{"@type":"PropertyValue","name":"JobSearcher","value":"37a38c84f9ef40aa41df4c98"},"url":"https://jobsearcher.com/jobs/37a38c84f9ef40aa41df4c98"}}