{"schemaVersion":"jobsearcher.job.v1","id":"375df5061789cd3a6a9d1f3d","url":"https://jobsearcher.com/jobs/375df5061789cd3a6a9d1f3d","canonicalUrl":"https://jobsearcher.com/jobs/375df5061789cd3a6a9d1f3d","title":"Hardware Engineering, Architect","description":"We Are:\nAt Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.\n\nYou Are:\nA seasoned engineer with over 15 years of experience in DDR/HBM SIPI engineering. You possess a deep understanding of high-speed interface signaling operations, including s-parameters, channel loss, crosstalk, equalization techniques, jitter, and power delivery modeling. Your expertise in signal and power integrity analysis methods, such as eye diagram construction through statistical modeling, return loss, impedance matching, and resonant system analysis, is unmatched.\nYou are proficient in using HFSS and Ansys tools, HSPICE, Raptor, and ADS. You excel at generating and communicating results, findings, conclusions, and recommendations within a design team and to external customers. Your knowledge in board-level construction and on-chip IO design operation allows you to work seamlessly across multi-site teams, communicating ideas, understanding problems, and finding solutions to create leading-edge designs.\nAs a team player, you communicate clearly and efficiently, leading issues to full closure independently. Your ability to track industry developments through activities at standards committees and memory vendor roadmaps ensures that you stay ahead of the curve in technological advancements.\n\nWhat You’ll Be Doing:\n\nPerform interconnect assessments using the latest modeling techniques to predict channel data rates and signal margins.\nAssess strategies for system performance optimization, including signal margins, power, and FFE, DFE, and CTLE equalization techniques.\nAssess power delivery systems to optimize power integrity for supply stability and jitter minimization.\nDocument findings in reports and design guidelines.\nCommunicate results and insights to design teams to improve PHY design.\nCommunicate results and recommendations to customers to enable them to optimize their system performance.\nInteract with design teams and customers to refine and apply signal and power analysis methods to refine strategies and address problems.\nUnderstand Synopsys’ DDR and HBM PHY roadmap and create strategies for improved performance.\nTrack industry developments through activities at standards committees and through memory vendor roadmaps.\n\nWhat You’ll Need:\n\nProven understanding of high-speed interface signaling operation, such as s-parameters, channel loss, crosstalk, equalization techniques, jitter, and power delivery modeling.\nWell-versed in signal and power delivery analysis methods, including eye diagram construction through statistical modeling, return loss, impedance matching, and resonant system analysis.\nAbility to use HFSS and Ansys tools, HSPICE, Raptor, and ADS.\nSkilled in generating and communicating results, findings, conclusions, and recommendations within a design team and to external customers.\nKnowledgeable in board-level construction and on-chip IO design operation.\n\nThe Impact You Will Have:\n\nEnhance the performance and reliability of high-speed interface designs.\nDrive improvements in system performance optimization techniques, contributing to lower power consumption and higher data rates.\nOptimize power delivery systems, ensuring supply stability and minimized jitter.\nProvide critical insights and recommendations that will shape the design and development of PHY components.\nEnable customers to achieve optimal system performance through your expert guidance.\nContribute to the advancement of SIPI methodologies and their adoption by customers.\nHelp refine strategies to address signal and power integrity challenges in cutting-edge technologies.\nInfluence the direction of Synopsys’ DDR and HBM PHY roadmap.\nStay at the forefront of industry developments, ensuring Synopsys remains a leader in technological innovation.\n\nWho You Are:\n\nA team player able to communicate clearly and efficiently.\nAbility to independently lead issues to full closure.\n\nThe Team You’ll Be A Part Of:\nThe R&D circuits team is tasked with providing SIPI solutions for the future DDR/HBM topologies and protocols, identifying key enablers, and providing support to early adopters or critical customers. We are also responsible for SIPI methodologies to be adopted by the customers and interconnect budgeting.\n#LI-NK4","company":"Synopsys","rawCompany":"synopsys","city":"Mountain View","state":"HI","isRemote":false,"isActive":false,"createdAt":"2026-08-03T18:57:23.153Z","occupations":[{"code":"17-2061.00","title":"Computer Hardware Engineers","slug":"computer-hardware-engineers"},{"code":"17-2072.00","title":"Electronics Engineers, Except Computer","slug":"electronics-engineers-except-computer"},{"code":"17-2199.00","title":"Engineers, All Other","slug":"engineers-all-other"}],"industries":[{"code":"334413","title":"Semiconductor and Related Device Manufacturing","slug":"semiconductor-and-related-device-manufacturing"},{"code":"541715","title":"Research and Development in the Physical, Engineering, and Life Sciences (except Nanotechnology and Biotechnology)","slug":"research-and-development-in-the-physical-engineering-and-life-sciences-except-nanotechnology-and-biotechnology"},{"code":"334111","title":"Electronic Computer Manufacturing","slug":"electronic-computer-manufacturing"}],"jobPosting":{"@context":"https://schema.org","@type":"JobPosting","title":"Hardware Engineering, Architect","description":"We Are:\nAt Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.\n\nYou Are:\nA seasoned engineer with over 15 years of experience in DDR/HBM SIPI engineering. You possess a deep understanding of high-speed interface signaling operations, including s-parameters, channel loss, crosstalk, equalization techniques, jitter, and power delivery modeling. Your expertise in signal and power integrity analysis methods, such as eye diagram construction through statistical modeling, return loss, impedance matching, and resonant system analysis, is unmatched.\nYou are proficient in using HFSS and Ansys tools, HSPICE, Raptor, and ADS. You excel at generating and communicating results, findings, conclusions, and recommendations within a design team and to external customers. Your knowledge in board-level construction and on-chip IO design operation allows you to work seamlessly across multi-site teams, communicating ideas, understanding problems, and finding solutions to create leading-edge designs.\nAs a team player, you communicate clearly and efficiently, leading issues to full closure independently. Your ability to track industry developments through activities at standards committees and memory vendor roadmaps ensures that you stay ahead of the curve in technological advancements.\n\nWhat You’ll Be Doing:\n\nPerform interconnect assessments using the latest modeling techniques to predict channel data rates and signal margins.\nAssess strategies for system performance optimization, including signal margins, power, and FFE, DFE, and CTLE equalization techniques.\nAssess power delivery systems to optimize power integrity for supply stability and jitter minimization.\nDocument findings in reports and design guidelines.\nCommunicate results and insights to design teams to improve PHY design.\nCommunicate results and recommendations to customers to enable them to optimize their system performance.\nInteract with design teams and customers to refine and apply signal and power analysis methods to refine strategies and address problems.\nUnderstand Synopsys’ DDR and HBM PHY roadmap and create strategies for improved performance.\nTrack industry developments through activities at standards committees and through memory vendor roadmaps.\n\nWhat You’ll Need:\n\nProven understanding of high-speed interface signaling operation, such as s-parameters, channel loss, crosstalk, equalization techniques, jitter, and power delivery modeling.\nWell-versed in signal and power delivery analysis methods, including eye diagram construction through statistical modeling, return loss, impedance matching, and resonant system analysis.\nAbility to use HFSS and Ansys tools, HSPICE, Raptor, and ADS.\nSkilled in generating and communicating results, findings, conclusions, and recommendations within a design team and to external customers.\nKnowledgeable in board-level construction and on-chip IO design operation.\n\nThe Impact You Will Have:\n\nEnhance the performance and reliability of high-speed interface designs.\nDrive improvements in system performance optimization techniques, contributing to lower power consumption and higher data rates.\nOptimize power delivery systems, ensuring supply stability and minimized jitter.\nProvide critical insights and recommendations that will shape the design and development of PHY components.\nEnable customers to achieve optimal system performance through your expert guidance.\nContribute to the advancement of SIPI methodologies and their adoption by customers.\nHelp refine strategies to address signal and power integrity challenges in cutting-edge technologies.\nInfluence the direction of Synopsys’ DDR and HBM PHY roadmap.\nStay at the forefront of industry developments, ensuring Synopsys remains a leader in technological innovation.\n\nWho You Are:\n\nA team player able to communicate clearly and efficiently.\nAbility to independently lead issues to full closure.\n\nThe Team You’ll Be A Part Of:\nThe R&D circuits team is tasked with providing SIPI solutions for the future DDR/HBM topologies and protocols, identifying key enablers, and providing support to early adopters or critical customers. We are also responsible for SIPI methodologies to be adopted by the customers and interconnect budgeting.\n#LI-NK4","datePosted":"2026-08-03T18:57:23.153Z","dateModified":"2026-08-03T18:57:23.153Z","hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://jobsearcher.com"},"jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Mountain View","addressRegion":"HI","addressCountry":"US"}},"identifier":{"@type":"PropertyValue","name":"JobSearcher","value":"375df5061789cd3a6a9d1f3d"},"url":"https://jobsearcher.com/jobs/375df5061789cd3a6a9d1f3d"}}