{"schemaVersion":"jobsearcher.job.v1","id":"2f7ac8a8a479715eaa5d5fde","url":"https://jobsearcher.com/jobs/2f7ac8a8a479715eaa5d5fde","canonicalUrl":"https://jobsearcher.com/jobs/2f7ac8a8a479715eaa5d5fde","title":"High-Speed Interconnect Senior Validation Engineer","description":"High-Speed Interconnect Senior Validation Engineer\nJoin to apply for the High-Speed Interconnect Senior Validation Engineer role at Intel Corporation.\n\nJob Details\n\nWe are seeking a High-Speed Interconnect Validation Engineer to lead end-to-end validation of next-generation data center and AI platform interconnects—including PCIe, CXL, and UALink—spanning node, rack, and large-scale cluster environments. This role is heavily focused on ensuring interoperability, performance, reliability, and standards compliance of high-speed I/O fabrics that power modern AI and HPC systems. The ideal candidate has deep technical knowledge of high-speed protocols, strong platform-level debug skills, and a passion for validating complex systems at scale.\n\nKey Responsibilities\n\nOwn validation strategy, test planning, and execution for PCIe, CXL, and UALink across silicon, platform, rack, and cluster configurations.\n\nDevelop comprehensive validation coverage for link training, error handling, fabric scaling, congestion, performance, and protocol compliance.\n\nPerform bring-up and debug of high-speed I/O subsystems using protocol analyzers, exercisers, and signal measurement tools.\n\nValidate interconnect behavior under AI/ML workloads, stress conditions, and multi-node traffic patterns.\n\nDrive interoperability testing across GPUs, accelerators, switches, storage, and memory devices from diverse ecosystem partners.\n\nCollaborate with silicon design, board design, firmware, and software teams to resolve complex cross-layer issues.\n\nBuild automation, diagnostics, and scaling frameworks to validate fabrics at rack-level and multi-rack cluster scale.\n\nAnalyze performance metrics, identify bottlenecks, and recommend architectural or firmware tuning for optimal interconnect efficiency.\n\nInfluence next‑generation high-speed I/O roadmap by providing data‑driven insights from validation cycles.\n\nEngage with hyperscalers, OEMs/ODMs, and industry partners to ensure end‑to‑end readiness for deployment.\n\nWhat You’ll Gain\n\nOpportunity to validate the fastest and most advanced interconnects powering modern AI systems.\n\nHands‑on experience from silicon bring‑up to rackscale cluster validation.\n\nInfluence the architecture and deployment readiness of next‑generation data center fabrics.\n\nQualifications\n\nMinimum Qualifications\n\nBachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 10+ years of experience.\n\n8+ years of experience in SoC and Validation.\n\nHands‑on experience validating high‑speed I/O standards such as PCIe Gen4/5/6, CXL 2.0/3.0, or UALink.\n\nSolid understanding of protocol layers, link training, flow control, and fabric management.\n\nExperience with high-speed debug tools (protocol analyzers, exercisers, oscilloscopes, BERTs).\n\nStrong system‑level debug skills across hardware, firmware, BIOS, OS, and drivers.\n\nFamiliarity with data center or AI platform architecture.\n\nPreferred Qualifications\n\nExperience validating large‑scale AI clusters, GPU/accelerator fabrics, or coherent memory pooling.\n\nDeep knowledge of CXL switching, memory expansion, and coherency models.\n\nExperience with SI/PI fundamentals and their impact on validation outcomes.\n\nFamiliarity with automation frameworks (Python, Jenkins, etc.) for multi-node testing.\n\nPrior collaboration with open standards bodies or hyperscale customers.\n\nRequirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.\n\nJob Type\n\nExperienced Hire\n\nShift\n\nShift 1 (United States of America)\n\nPrimary Location\n\nUS, Oregon, Hillsboro\n\nAdditional Locations\n\nUS, California, Santa Clara\n\nBusiness Group\n\nAt the Data Center Group (DCG), we are committed to delivering exceptional products and delighting our customers. We offer both broad-market Xeon-based solutions and custom x86-based products, ensuring tailored innovation for diverse needs across general-purpose compute, web services, HPC, and AI-accelerated systems. Our charter encompasses defining business strategy and roadmaps, product management, developing ecosystems and business opportunities, delivering strong financial performance, and reinvigorating x86 leadership. Join us as we transform the data center segment through workload-driven leadership products and close collaboration with our partners.\n\nPosting Statement\n\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\n\nPosition of Trust\n\nThis role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law) extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.\n\nBenefits\n\nWe offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: Benefits Page .\n\nAnnual Salary Range for jobs which could be performed in the US 214,730.00 USD - 303,140.00 USD\n\nWork Model for this Role\n\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on‑site at their assigned Intel site and off‑site. Job posting details (such as work model, location or time type) are subject to change.\n\nSeniority level\nMid‑Senior level\n\nEmployment type\nFull‑time\n\nJob function\nQuality Assurance\n\nIndustries\nSemiconductor Manufacturing\n\n#J-18808-Ljbffr","company":"Intel","rawCompany":"intel","city":"Hillsboro","state":"IL","isRemote":false,"isActive":false,"createdAt":"2026-04-09T07:56:30.483Z","occupations":[{"code":"17-2112.02","title":"Validation Engineers","slug":"validation-engineers"},{"code":"17-2061.00","title":"Computer Hardware Engineers","slug":"computer-hardware-engineers"},{"code":"15-1299.08","title":"Computer Systems Engineers/Architects","slug":"computer-systems-engineers-architects"}],"industries":[{"code":"541512","title":"Computer Systems Design Services","slug":"computer-systems-design-services"},{"code":"334111","title":"Electronic Computer Manufacturing","slug":"electronic-computer-manufacturing"},{"code":"518210","title":"Computing Infrastructure Providers, Data Processing, Web Hosting, and Related Services","slug":"computing-infrastructure-providers-data-processing-web-hosting-and-related-services"}],"jobPosting":{"@context":"https://schema.org","@type":"JobPosting","title":"High-Speed Interconnect Senior Validation Engineer","description":"High-Speed Interconnect Senior Validation Engineer\nJoin to apply for the High-Speed Interconnect Senior Validation Engineer role at Intel Corporation.\n\nJob Details\n\nWe are seeking a High-Speed Interconnect Validation Engineer to lead end-to-end validation of next-generation data center and AI platform interconnects—including PCIe, CXL, and UALink—spanning node, rack, and large-scale cluster environments. This role is heavily focused on ensuring interoperability, performance, reliability, and standards compliance of high-speed I/O fabrics that power modern AI and HPC systems. The ideal candidate has deep technical knowledge of high-speed protocols, strong platform-level debug skills, and a passion for validating complex systems at scale.\n\nKey Responsibilities\n\nOwn validation strategy, test planning, and execution for PCIe, CXL, and UALink across silicon, platform, rack, and cluster configurations.\n\nDevelop comprehensive validation coverage for link training, error handling, fabric scaling, congestion, performance, and protocol compliance.\n\nPerform bring-up and debug of high-speed I/O subsystems using protocol analyzers, exercisers, and signal measurement tools.\n\nValidate interconnect behavior under AI/ML workloads, stress conditions, and multi-node traffic patterns.\n\nDrive interoperability testing across GPUs, accelerators, switches, storage, and memory devices from diverse ecosystem partners.\n\nCollaborate with silicon design, board design, firmware, and software teams to resolve complex cross-layer issues.\n\nBuild automation, diagnostics, and scaling frameworks to validate fabrics at rack-level and multi-rack cluster scale.\n\nAnalyze performance metrics, identify bottlenecks, and recommend architectural or firmware tuning for optimal interconnect efficiency.\n\nInfluence next‑generation high-speed I/O roadmap by providing data‑driven insights from validation cycles.\n\nEngage with hyperscalers, OEMs/ODMs, and industry partners to ensure end‑to‑end readiness for deployment.\n\nWhat You’ll Gain\n\nOpportunity to validate the fastest and most advanced interconnects powering modern AI systems.\n\nHands‑on experience from silicon bring‑up to rackscale cluster validation.\n\nInfluence the architecture and deployment readiness of next‑generation data center fabrics.\n\nQualifications\n\nMinimum Qualifications\n\nBachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 10+ years of experience.\n\n8+ years of experience in SoC and Validation.\n\nHands‑on experience validating high‑speed I/O standards such as PCIe Gen4/5/6, CXL 2.0/3.0, or UALink.\n\nSolid understanding of protocol layers, link training, flow control, and fabric management.\n\nExperience with high-speed debug tools (protocol analyzers, exercisers, oscilloscopes, BERTs).\n\nStrong system‑level debug skills across hardware, firmware, BIOS, OS, and drivers.\n\nFamiliarity with data center or AI platform architecture.\n\nPreferred Qualifications\n\nExperience validating large‑scale AI clusters, GPU/accelerator fabrics, or coherent memory pooling.\n\nDeep knowledge of CXL switching, memory expansion, and coherency models.\n\nExperience with SI/PI fundamentals and their impact on validation outcomes.\n\nFamiliarity with automation frameworks (Python, Jenkins, etc.) for multi-node testing.\n\nPrior collaboration with open standards bodies or hyperscale customers.\n\nRequirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.\n\nJob Type\n\nExperienced Hire\n\nShift\n\nShift 1 (United States of America)\n\nPrimary Location\n\nUS, Oregon, Hillsboro\n\nAdditional Locations\n\nUS, California, Santa Clara\n\nBusiness Group\n\nAt the Data Center Group (DCG), we are committed to delivering exceptional products and delighting our customers. We offer both broad-market Xeon-based solutions and custom x86-based products, ensuring tailored innovation for diverse needs across general-purpose compute, web services, HPC, and AI-accelerated systems. Our charter encompasses defining business strategy and roadmaps, product management, developing ecosystems and business opportunities, delivering strong financial performance, and reinvigorating x86 leadership. Join us as we transform the data center segment through workload-driven leadership products and close collaboration with our partners.\n\nPosting Statement\n\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\n\nPosition of Trust\n\nThis role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law) extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.\n\nBenefits\n\nWe offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: Benefits Page .\n\nAnnual Salary Range for jobs which could be performed in the US 214,730.00 USD - 303,140.00 USD\n\nWork Model for this Role\n\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on‑site at their assigned Intel site and off‑site. Job posting details (such as work model, location or time type) are subject to change.\n\nSeniority level\nMid‑Senior level\n\nEmployment type\nFull‑time\n\nJob function\nQuality Assurance\n\nIndustries\nSemiconductor Manufacturing\n\n#J-18808-Ljbffr","datePosted":"2026-04-09T07:56:30.483Z","dateModified":"2026-04-09T07:56:30.483Z","hiringOrganization":{"@type":"Organization","name":"Intel","sameAs":"https://jobsearcher.com"},"jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Hillsboro","addressRegion":"IL","addressCountry":"US"}},"identifier":{"@type":"PropertyValue","name":"JobSearcher","value":"2f7ac8a8a479715eaa5d5fde"},"url":"https://jobsearcher.com/jobs/2f7ac8a8a479715eaa5d5fde"}}