{"schemaVersion":"jobsearcher.job.v1","id":"2f3658c0f993be23ab1694ee","url":"https://jobsearcher.com/jobs/2f3658c0f993be23ab1694ee","canonicalUrl":"https://jobsearcher.com/jobs/2f3658c0f993be23ab1694ee","title":"Senior Technical Lead - Silicon Platform Validation, Python","description":"Senior Technical Lead - Silicon Platform Validation, Python Senior Technical Lead - Silicon Platform Validation, Python United States Job Description Senior Technical Lead - Silicon Platform Validation, Python Santa Clara, California\r\nJob SummaryWe are looking for an experienced SoC Validation Engineer to drive end-to-end validation of complex System-on-Chip (SoC) designs across both pre-silicon and post-silicon phases. The ideal candidate brings deep domain expertise in SoC IP subsystems — including Clock, Reset, Ethernet, I/O controllers, and related infrastructure IPs — with proven ability to develop test strategies, execute validation plans, and root-cause failures from simulation through first silicon and production.\r\nKey ResponsibilitiesPre-Silicon ValidationDevelop comprehensive verification and validation plans for SoC-level IP subsystems includingClock Generation/Distribution (PLLs, clock muxes, dividers) ,Reset Architecture ,Ethernet MAC/PHY , andI/O interfaces (GPIO, I2C, SPI, UART, JTAG)\r\nCreate and execute directed and constrained-random tests targeting IP integration, connectivity, and functional correctness at the SoC level\r\nVerify clock domain crossings (CDC), reset sequencing, and power-on reset (POR) behavior\r\nValidate Ethernet data path integrity, link negotiation, and MAC-to-PHY (MII/RGMII/SGMII) interfaces\r\nPerformfunctional coverage analysisand drive coverage closure across IP blocks\r\nCollaborate with design and architecture teams on RTL debug, assertions, and specification reviews\r\nExecute validation onemulation/FPGA prototyping platforms(Palladium, Veloce, Protium) for early software/firmware integration\r\nPost-Silicon ValidationBring up and validate SoC IPs on first silicon and platform boards\r\nDevelop and execute post-silicon test plans covering:Clock:PLL lock times, frequency accuracy, jitter characterization, clock switching, glitch-free mux transitions\r\nReset:Reset assertion/de-assertion sequencing, warm/cold reset flows, watchdog timer resets, brown-out detection\r\nEthernet:Link bring-up, auto-negotiation, packet integrity (CRC/FCS), throughput/latency, loopback testing, PTP/IEEE 1588 timestamping\r\nI/O:Pin mux configuration, drive strength, voltage levels, protocol compliance (I2C/SPI/UART timing), interrupt routingDebug silicon failures usingoscilloscopes, logic analyzers, protocol analyzers, JTAG/DFx , and embedded trace tools\r\nPerform root-cause analysis of post-silicon bugs and drive resolution with design and firmware teams\r\nCharacterize IP performance under varying voltage, frequency, and temperature (VFT) conditions\r\nDevelop and maintainautomated test frameworksfor regression and production testing\r\nCollaborate with platform, firmware, BSP, and driver teams on system-level integration and debug\r\nGeneralAuthor and maintain validation documentation: test plans, debug reports, coverage metrics, and known-issue databases\r\nDevelopPython/Perl/Tcl scriptsfor test automation, log parsing, and result analysis\r\nParticipate in silicon bring-up triage, failure analysis, and bug review meetings\r\nMentor junior engineers and drive process improvements in validation methodology\r\nInterface with IP vendors for third-party IP integration, compliance, and issue resolution\r\nSkill RequirementsRequired QualificationsEducation:B.S./M.S./Ph.D. in Electrical Engineering, Computer Engineering, or related field\r\nExperience:4–10+ years in SoC validation (pre-silicon and/or post-silicon)\r\nDeep understanding ofSoC architectureand IP integration concepts\r\nMaximum Salary (US): 148000 Minimum Salary (US): 78000\r\nWhy HCLTech?At HCLTech, you'll supercharge your potential. You'll find your career. And you'll find your spark. All at a place that knows that helping its customers stay on top starts by putting its people first.\r\nHCLTech is a global technology company, home to more than 223,000 people across 60 countries, delivering industry-leading capabilities centered around digital, engineering, cloud and AI, powered by a broad portfolio of technology services and products. We work with clients across all major verticals, providing industry solutions for Financial Services, Manufacturing, Life Sciences and Healthcare, Technology and Services, Telecom and Media, Retail and CPG, and Public Services. Consolidated revenues as of 12 months ending June 2026totaled $14.8billion.\r\nCompensation and BenefitsA candidate’s pay within the range will depend on their skills, experience, education, and other factors permitted by law. This role may also be eligible for performance-based bonuses subject to company policies. In addition, this role is eligible for the following benefits subject to company policies: medical, dental, vision, pharmacy, life, accidental death & dismemberment, and disability insurance; employee assistance program; 401(k) retirement plan; 10 days of paid time off per year (some positions are eligible for need-based leave with no designated number of leave days per year); and 10 paid holidays per year.#J-18808-Ljbffr","company":"Hcl Technologies","rawCompany":"hcl technologies","city":"Santa Clara","state":"CA","isRemote":false,"isActive":false,"createdAt":"2026-10-04T01:24:46.780Z","occupations":[{"code":"17-2112.02","title":"Validation Engineers","slug":"validation-engineers"},{"code":"17-2072.00","title":"Electronics Engineers, Except Computer","slug":"electronics-engineers-except-computer"},{"code":"17-2061.00","title":"Computer Hardware Engineers","slug":"computer-hardware-engineers"}],"industries":[{"code":"541512","title":"Computer Systems Design Services","slug":"computer-systems-design-services"},{"code":"334413","title":"Semiconductor and Related Device Manufacturing","slug":"semiconductor-and-related-device-manufacturing"},{"code":"334419","title":"Other Electronic Component Manufacturing","slug":"other-electronic-component-manufacturing"}],"jobPosting":{"@context":"https://schema.org","@type":"JobPosting","title":"Senior Technical Lead - Silicon Platform Validation, Python","description":"Senior Technical Lead - Silicon Platform Validation, Python Senior Technical Lead - Silicon Platform Validation, Python United States Job Description Senior Technical Lead - Silicon Platform Validation, Python Santa Clara, California\r\nJob SummaryWe are looking for an experienced SoC Validation Engineer to drive end-to-end validation of complex System-on-Chip (SoC) designs across both pre-silicon and post-silicon phases. The ideal candidate brings deep domain expertise in SoC IP subsystems — including Clock, Reset, Ethernet, I/O controllers, and related infrastructure IPs — with proven ability to develop test strategies, execute validation plans, and root-cause failures from simulation through first silicon and production.\r\nKey ResponsibilitiesPre-Silicon ValidationDevelop comprehensive verification and validation plans for SoC-level IP subsystems includingClock Generation/Distribution (PLLs, clock muxes, dividers) ,Reset Architecture ,Ethernet MAC/PHY , andI/O interfaces (GPIO, I2C, SPI, UART, JTAG)\r\nCreate and execute directed and constrained-random tests targeting IP integration, connectivity, and functional correctness at the SoC level\r\nVerify clock domain crossings (CDC), reset sequencing, and power-on reset (POR) behavior\r\nValidate Ethernet data path integrity, link negotiation, and MAC-to-PHY (MII/RGMII/SGMII) interfaces\r\nPerformfunctional coverage analysisand drive coverage closure across IP blocks\r\nCollaborate with design and architecture teams on RTL debug, assertions, and specification reviews\r\nExecute validation onemulation/FPGA prototyping platforms(Palladium, Veloce, Protium) for early software/firmware integration\r\nPost-Silicon ValidationBring up and validate SoC IPs on first silicon and platform boards\r\nDevelop and execute post-silicon test plans covering:Clock:PLL lock times, frequency accuracy, jitter characterization, clock switching, glitch-free mux transitions\r\nReset:Reset assertion/de-assertion sequencing, warm/cold reset flows, watchdog timer resets, brown-out detection\r\nEthernet:Link bring-up, auto-negotiation, packet integrity (CRC/FCS), throughput/latency, loopback testing, PTP/IEEE 1588 timestamping\r\nI/O:Pin mux configuration, drive strength, voltage levels, protocol compliance (I2C/SPI/UART timing), interrupt routingDebug silicon failures usingoscilloscopes, logic analyzers, protocol analyzers, JTAG/DFx , and embedded trace tools\r\nPerform root-cause analysis of post-silicon bugs and drive resolution with design and firmware teams\r\nCharacterize IP performance under varying voltage, frequency, and temperature (VFT) conditions\r\nDevelop and maintainautomated test frameworksfor regression and production testing\r\nCollaborate with platform, firmware, BSP, and driver teams on system-level integration and debug\r\nGeneralAuthor and maintain validation documentation: test plans, debug reports, coverage metrics, and known-issue databases\r\nDevelopPython/Perl/Tcl scriptsfor test automation, log parsing, and result analysis\r\nParticipate in silicon bring-up triage, failure analysis, and bug review meetings\r\nMentor junior engineers and drive process improvements in validation methodology\r\nInterface with IP vendors for third-party IP integration, compliance, and issue resolution\r\nSkill RequirementsRequired QualificationsEducation:B.S./M.S./Ph.D. in Electrical Engineering, Computer Engineering, or related field\r\nExperience:4–10+ years in SoC validation (pre-silicon and/or post-silicon)\r\nDeep understanding ofSoC architectureand IP integration concepts\r\nMaximum Salary (US): 148000 Minimum Salary (US): 78000\r\nWhy HCLTech?At HCLTech, you'll supercharge your potential. You'll find your career. And you'll find your spark. All at a place that knows that helping its customers stay on top starts by putting its people first.\r\nHCLTech is a global technology company, home to more than 223,000 people across 60 countries, delivering industry-leading capabilities centered around digital, engineering, cloud and AI, powered by a broad portfolio of technology services and products. We work with clients across all major verticals, providing industry solutions for Financial Services, Manufacturing, Life Sciences and Healthcare, Technology and Services, Telecom and Media, Retail and CPG, and Public Services. Consolidated revenues as of 12 months ending June 2026totaled $14.8billion.\r\nCompensation and BenefitsA candidate’s pay within the range will depend on their skills, experience, education, and other factors permitted by law. This role may also be eligible for performance-based bonuses subject to company policies. In addition, this role is eligible for the following benefits subject to company policies: medical, dental, vision, pharmacy, life, accidental death & dismemberment, and disability insurance; employee assistance program; 401(k) retirement plan; 10 days of paid time off per year (some positions are eligible for need-based leave with no designated number of leave days per year); and 10 paid holidays per year.#J-18808-Ljbffr","datePosted":"2026-10-04T01:24:46.780Z","dateModified":"2026-10-04T01:24:46.780Z","hiringOrganization":{"@type":"Organization","name":"Hcl Technologies","sameAs":"https://jobsearcher.com"},"jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Santa Clara","addressRegion":"CA","addressCountry":"US"}},"identifier":{"@type":"PropertyValue","name":"JobSearcher","value":"2f3658c0f993be23ab1694ee"},"url":"https://jobsearcher.com/jobs/2f3658c0f993be23ab1694ee"}}