RTL Lead

VirtualOnsite: San Jose, CA (Local)USC and GCPrincipal RTL Lead – High-Speed Ethernet ASIC (400G/800G)Rate: DOEJD:We are hiring a Principal RTL Lead to drive the design and development of next-generation Ethernet subsystems for custom ASIC silicon , supporting 400G/800G+ data center infrastructure This is a highly technical, hands-on role focused on solving complex challenges in high-speed digital design, multi-lane data processing, and Ethernet protocol implementation =' Key ResponsibilitiesDefine micro-architecture for high-bandwidth datapaths and control logicLead SystemVerilog RTL design for Ethernet subsystemsImplement IEEE 802.3 standards , including:RS-FEC (Reed-Solomon)Multi-Lane Distribution (MLD)Auto-Negotiation / Link Training (AN/LT)Solve complex design challenges:Wide datapaths (1024-bit+)Timing closure at high frequenciesClock domain crossing (CDC) across asynchronous boundariesLead integration of SerDes IP and ensure PHY ? MAC interoperabilityDrive best practices across:Lint / CDC / RDCPower optimization (UPF)Design quality for first-pass silicon successRequired Experience10+ years in ASIC RTL design (SystemVerilog)Proven track record of multiple successful tape-outs (7nm / 5nm / 3nm preferred)Deep expertise in high-speed Ethernet (100G / 400G / 800G)Strong understanding of MAC / PCS / FEC layersExperience across full ASIC front-end flow (architecture ? RTL ? verification ? bring-up)Ability to lead subsystem design and mentor engineersP Nice to HaveIEEE 1588 (PTP) hardware timestampingPCIe Gen5/6 or CXLPython / Perl scripting for design automationExperience working closely with physical design teams (timing / congestion)