{"schemaVersion":"jobsearcher.job.v1","id":"2c827098e6c0a119718c11fb","url":"https://jobsearcher.com/jobs/2c827098e6c0a119718c11fb","canonicalUrl":"https://jobsearcher.com/jobs/2c827098e6c0a119718c11fb","title":"RTL Lead","description":"VirtualOnsite: San Jose, CA (Local)USC and GCPrincipal RTL Lead – High-Speed Ethernet ASIC (400G/800G)Rate: DOEJD:We are hiring a Principal RTL Lead to drive the design and development of next-generation Ethernet subsystems for custom ASIC silicon , supporting 400G/800G+ data center infrastructure This is a highly technical, hands-on role focused on solving complex challenges in high-speed digital design, multi-lane data processing, and Ethernet protocol implementation =' Key ResponsibilitiesDefine micro-architecture for high-bandwidth datapaths and control logicLead SystemVerilog RTL design for Ethernet subsystemsImplement IEEE 802.3 standards , including:RS-FEC (Reed-Solomon)Multi-Lane Distribution (MLD)Auto-Negotiation / Link Training (AN/LT)Solve complex design challenges:Wide datapaths (1024-bit+)Timing closure at high frequenciesClock domain crossing (CDC) across asynchronous boundariesLead integration of SerDes IP and ensure PHY ? MAC interoperabilityDrive best practices across:Lint / CDC / RDCPower optimization (UPF)Design quality for first-pass silicon successRequired Experience10+ years in ASIC RTL design (SystemVerilog)Proven track record of multiple successful tape-outs (7nm / 5nm / 3nm preferred)Deep expertise in high-speed Ethernet (100G / 400G / 800G)Strong understanding of MAC / PCS / FEC layersExperience across full ASIC front-end flow (architecture ? RTL ? verification ? bring-up)Ability to lead subsystem design and mentor engineersP Nice to HaveIEEE 1588 (PTP) hardware timestampingPCIe Gen5/6 or CXLPython / Perl scripting for design automationExperience working closely with physical design teams (timing / congestion)","company":"ShiftCode Analytics","rawCompany":"shiftcode analytics","city":"San Jose","state":"CA","isRemote":false,"isActive":false,"createdAt":"2026-05-14T03:36:17.155Z","occupations":[{"code":"15-1299.08","title":"Computer Systems Engineers/Architects","slug":"computer-systems-engineers-architects"},{"code":"15-1241.00","title":"Computer Network Architects","slug":"computer-network-architects"},{"code":"17-2061.00","title":"Computer Hardware Engineers","slug":"computer-hardware-engineers"}],"industries":[{"code":"541512","title":"Computer Systems Design Services","slug":"computer-systems-design-services"},{"code":"334413","title":"Semiconductor and Related Device Manufacturing","slug":"semiconductor-and-related-device-manufacturing"},{"code":"334111","title":"Electronic Computer Manufacturing","slug":"electronic-computer-manufacturing"}],"jobPosting":{"@context":"https://schema.org","@type":"JobPosting","title":"RTL Lead","description":"VirtualOnsite: San Jose, CA (Local)USC and GCPrincipal RTL Lead – High-Speed Ethernet ASIC (400G/800G)Rate: DOEJD:We are hiring a Principal RTL Lead to drive the design and development of next-generation Ethernet subsystems for custom ASIC silicon , supporting 400G/800G+ data center infrastructure This is a highly technical, hands-on role focused on solving complex challenges in high-speed digital design, multi-lane data processing, and Ethernet protocol implementation =' Key ResponsibilitiesDefine micro-architecture for high-bandwidth datapaths and control logicLead SystemVerilog RTL design for Ethernet subsystemsImplement IEEE 802.3 standards , including:RS-FEC (Reed-Solomon)Multi-Lane Distribution (MLD)Auto-Negotiation / Link Training (AN/LT)Solve complex design challenges:Wide datapaths (1024-bit+)Timing closure at high frequenciesClock domain crossing (CDC) across asynchronous boundariesLead integration of SerDes IP and ensure PHY ? MAC interoperabilityDrive best practices across:Lint / CDC / RDCPower optimization (UPF)Design quality for first-pass silicon successRequired Experience10+ years in ASIC RTL design (SystemVerilog)Proven track record of multiple successful tape-outs (7nm / 5nm / 3nm preferred)Deep expertise in high-speed Ethernet (100G / 400G / 800G)Strong understanding of MAC / PCS / FEC layersExperience across full ASIC front-end flow (architecture ? RTL ? verification ? bring-up)Ability to lead subsystem design and mentor engineersP Nice to HaveIEEE 1588 (PTP) hardware timestampingPCIe Gen5/6 or CXLPython / Perl scripting for design automationExperience working closely with physical design teams (timing / congestion)","datePosted":"2026-05-14T03:36:17.155Z","dateModified":"2026-05-14T03:36:17.155Z","hiringOrganization":{"@type":"Organization","name":"ShiftCode Analytics","sameAs":"https://jobsearcher.com"},"jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"San Jose","addressRegion":"CA","addressCountry":"US"}},"identifier":{"@type":"PropertyValue","name":"JobSearcher","value":"2c827098e6c0a119718c11fb"},"url":"https://jobsearcher.com/jobs/2c827098e6c0a119718c11fb"}}