{"schemaVersion":"jobsearcher.job.v1","id":"2b0236ca60aad09dd0bd2dfe","url":"https://jobsearcher.com/jobs/2b0236ca60aad09dd0bd2dfe","canonicalUrl":"https://jobsearcher.com/jobs/2b0236ca60aad09dd0bd2dfe","title":"Engineer, Silicon Validation","description":"Engineer: Silicon Validation\n\nLocation: San Jose (on-site)\n\nAyar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light instead of electricity to move data faster, further, and with a fraction of the energy needed to fuel the explosive growth of AI models.\n\nBacked by industry giants like NVIDIA, AMD and Intel and manufactured in partnership with the world’s leading semiconductor ecosystem, Ayar Labs’ co-packaged optics solution is key to unleashing next-generation AI scale-up architectures.\n\nIn this role, you will own the silicon bring up and validation of our optical chiplets. You will execute post-silicon bringup and characterization across SerDes, photonic, and mixed-signal blocks, building the test infrastructure and automation that ensures our products meet and exceed specification before customer deployment.\n\nEssential Functions\nPerform initial power-on and bringup of new silicon tape-outs, including boot sequence validation, clock/power domain verification, and initial functionality tests.\nPerform functional and electrical characterization of high-speed SerDes interfaces, photonic control blocks, and mixed signal blocks. Define and execute test plans at both block and chip level.\nUse lab test equipment (BERT, oscilloscope/DCA, OSA, signal generators) to characterize signal integrity, eye diagrams, BER, jitter, and optical performance metrics.\nDevelop and maintain Python-based test scripts and automation frameworks for regression and characterization testing.\nSystematically investigate silicon anomalies and failures; collaborate with design and firmware engineers to develop and verify fixes.\nWrite clear test plans, validation reports, and signoff documentation; communicate findings to cross-functional teams.\nPartner with firmware, analog/mixed-signal, digital, and systems engineering teams across the full product development cycle.\n\nBasic Qualifications\nBachelor's degree in Electrical Engineering or related field with 1+ years of relevant industry experience.\nHands-on experience with post-silicon bringup and validation of high-speed SoC or mixed-signal devices.\nWorking knowledge of SerDes PHY operation and characterization, including NRZ and/or PAM-4 signaling.\nProficiency with lab equipment used for high-speed characterization: BERT, oscilloscopes, signal analyzers.\nProficiency in Python for test scripting and data analysis.\nStrong troubleshooting skills and ability to work independently in a lab environment.\nProficiency with version control (Git) and software development environments.\n\n Preferred Qualifications\nExperience with photonic device or electro-optic system characterization and validation.\nFamiliarity with optical measurement equipment (OSA, optical power meters, lasers).\nExperience with high-speed serial standards: Ethernet (100G+), PCIe, OIF CEI.\nExperience with board-level debug and hardware bring-up using JTAG or I2C/SPI interfaces.\n\nSalary range: $135,000 - $160,000\n\nNOTE TO RECRUITERS:\nPrincipals only. We are not accepting resumes from recruiters for this position. Remuneration for recruiting activities is only applicable subject to a signed and executed agreement between the parties. Please don’t send candidates to Ayar Labs, and do not contact our managers.\n\nAyar Labs is an Equal Opportunity Employer and is strongly committed to all policies which will afford equal opportunity employment to all qualified persons without regard to age, sex, national origin, race, color, ethnicity, creed, religion, gender identity, sexual orientation, disability, veteran status, or any other characteristic protected by law. It is the policy of Ayar Labs to provide reasonable accommodation when requested by a qualified applicant or employee with a disability, unless such accommodation would cause an undue hardship. Veterans are more than welcome and encouraged to apply.","company":"Ayar Labs","rawCompany":"ayar labs","city":"San Jose","state":"CA","isRemote":false,"isActive":false,"createdAt":"2026-08-19T13:26:31.650Z","occupations":[{"code":"17-2112.02","title":"Validation Engineers","slug":"validation-engineers"},{"code":"17-2072.00","title":"Electronics Engineers, Except Computer","slug":"electronics-engineers-except-computer"},{"code":"17-2199.00","title":"Engineers, All Other","slug":"engineers-all-other"}],"industries":[{"code":"334413","title":"Semiconductor and Related Device Manufacturing","slug":"semiconductor-and-related-device-manufacturing"},{"code":"541715","title":"Research and Development in the Physical, Engineering, and Life Sciences (except Nanotechnology and Biotechnology)","slug":"research-and-development-in-the-physical-engineering-and-life-sciences-except-nanotechnology-and-biotechnology"},{"code":"334419","title":"Other Electronic Component Manufacturing","slug":"other-electronic-component-manufacturing"}],"jobPosting":{"@context":"https://schema.org","@type":"JobPosting","title":"Engineer, Silicon Validation","description":"Engineer: Silicon Validation\n\nLocation: San Jose (on-site)\n\nAyar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light instead of electricity to move data faster, further, and with a fraction of the energy needed to fuel the explosive growth of AI models.\n\nBacked by industry giants like NVIDIA, AMD and Intel and manufactured in partnership with the world’s leading semiconductor ecosystem, Ayar Labs’ co-packaged optics solution is key to unleashing next-generation AI scale-up architectures.\n\nIn this role, you will own the silicon bring up and validation of our optical chiplets. You will execute post-silicon bringup and characterization across SerDes, photonic, and mixed-signal blocks, building the test infrastructure and automation that ensures our products meet and exceed specification before customer deployment.\n\nEssential Functions\nPerform initial power-on and bringup of new silicon tape-outs, including boot sequence validation, clock/power domain verification, and initial functionality tests.\nPerform functional and electrical characterization of high-speed SerDes interfaces, photonic control blocks, and mixed signal blocks. Define and execute test plans at both block and chip level.\nUse lab test equipment (BERT, oscilloscope/DCA, OSA, signal generators) to characterize signal integrity, eye diagrams, BER, jitter, and optical performance metrics.\nDevelop and maintain Python-based test scripts and automation frameworks for regression and characterization testing.\nSystematically investigate silicon anomalies and failures; collaborate with design and firmware engineers to develop and verify fixes.\nWrite clear test plans, validation reports, and signoff documentation; communicate findings to cross-functional teams.\nPartner with firmware, analog/mixed-signal, digital, and systems engineering teams across the full product development cycle.\n\nBasic Qualifications\nBachelor's degree in Electrical Engineering or related field with 1+ years of relevant industry experience.\nHands-on experience with post-silicon bringup and validation of high-speed SoC or mixed-signal devices.\nWorking knowledge of SerDes PHY operation and characterization, including NRZ and/or PAM-4 signaling.\nProficiency with lab equipment used for high-speed characterization: BERT, oscilloscopes, signal analyzers.\nProficiency in Python for test scripting and data analysis.\nStrong troubleshooting skills and ability to work independently in a lab environment.\nProficiency with version control (Git) and software development environments.\n\n Preferred Qualifications\nExperience with photonic device or electro-optic system characterization and validation.\nFamiliarity with optical measurement equipment (OSA, optical power meters, lasers).\nExperience with high-speed serial standards: Ethernet (100G+), PCIe, OIF CEI.\nExperience with board-level debug and hardware bring-up using JTAG or I2C/SPI interfaces.\n\nSalary range: $135,000 - $160,000\n\nNOTE TO RECRUITERS:\nPrincipals only. We are not accepting resumes from recruiters for this position. Remuneration for recruiting activities is only applicable subject to a signed and executed agreement between the parties. Please don’t send candidates to Ayar Labs, and do not contact our managers.\n\nAyar Labs is an Equal Opportunity Employer and is strongly committed to all policies which will afford equal opportunity employment to all qualified persons without regard to age, sex, national origin, race, color, ethnicity, creed, religion, gender identity, sexual orientation, disability, veteran status, or any other characteristic protected by law. It is the policy of Ayar Labs to provide reasonable accommodation when requested by a qualified applicant or employee with a disability, unless such accommodation would cause an undue hardship. Veterans are more than welcome and encouraged to apply.","datePosted":"2026-08-19T13:26:31.650Z","dateModified":"2026-08-19T13:26:31.650Z","hiringOrganization":{"@type":"Organization","name":"Ayar Labs","sameAs":"https://jobsearcher.com"},"jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"San Jose","addressRegion":"CA","addressCountry":"US"}},"identifier":{"@type":"PropertyValue","name":"JobSearcher","value":"2b0236ca60aad09dd0bd2dfe"},"url":"https://jobsearcher.com/jobs/2b0236ca60aad09dd0bd2dfe"}}