{"schemaVersion":"jobsearcher.job.v1","id":"269cd0a2cb0982ced9bb17de","url":"https://jobsearcher.com/jobs/269cd0a2cb0982ced9bb17de","canonicalUrl":"https://jobsearcher.com/jobs/269cd0a2cb0982ced9bb17de","title":"Principle Hardware Design Engineer - Systems Engineering","description":"Job Summary\n\nAs a Hardware Design Principal Engineer, you'll be a member of the Central Engineering business group. If you picture it as a wheel, Central Engineering is the center hub providing IP to be used by all the other spokes on that wheel, including Automotive, Storage, Security, and Networking. You'll be part of the printed circuit board (PCB) engineering team designing boards for many different groups. Additionally, you will be designing more complex chips and boards than our competitors, for higher speeds than anyone else. We're on the leading edge of this technology and you'll love being a part of this.\n\nThe Signal Integrity Engineering candidate within the Marlborough Design Center will have opportunity to contribute to design, implementation, and check out of critical SOC validation boards. This includes setting SI specifications, SI implementation guidelines for internal and external design teams, and simulation of the design to ensure high quality results. Additional opportunities include collaboration with the package design and signal integrity teams to ensure package and board parameters are well understood. This role is for an individual contributor who will join a diverse hardware and software group that owns development and execution of package and validation board design and implementation.\n\nRequired Skills, Experience, and Knowledge\n\nHigh speed diff pair design.\n\nPCIE Gen4 or PCIE Gen5 (PAM-4 okay too).\n\nExperience with reference board design for chip validation.\n\nKnowledge of PCB design issues associated with high-speed diff pair.\n\nPower controller design – low voltage, high current, multi-phase SMPS.\n\nExperience with Power Integrity analysis.\n\nKnowledge of SI tools – Sigrity, SI Soft, HFSS.\n\nComponent Selection.\n\nSchematic capture and PCB Layout tools (Prefer Cadence Concept).\n\nCloud compute systems.\n\nPCIe Protocols.\n\nClock generation and distribution.\n\nFamiliar with Mechanical design concepts.\n\nRole & Responsibilities\n\nDesign Reference board for PCIe Gen5/6 chip.\n\nSelect and implement power scheme.\n\nCapture Schematic.\n\nWork with PCB Layout house.\n\nCreate enterprise server reference systems, using PCIe Gen5 CEM sockets, and EDSFF.\n\nWork with customers to assist with their designs, and/or implement their designs.\n\nWork with RTL team to understand and implement various features and interfaces.\n\nProvide for programming of various memories.\n\nParticipate in bring and debug of chips.\n\nMake decisions about reference designs, including connectors, cables.\n\nWork with external vendors for problems, and completing their designs.\n\nWork with SI engineers.\n\nWork with chip package vendor for package design input.\n\nKey Requirements\n\nBachelor's degree in Computer Science, Electrical Engineering or related fields and 5-10 years of related professional experience. Master's degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3-5 years of experience.\n\nExperience as Lead Signal Integrity Engineer.\n\nStrong understanding of EM fundamentals. Modeling and analysis of transmission lines, via structures, high-speed connectors, and complex BGA packages.\n\nProficiency in 2D/3D EM tools such as Sigrity Suite or Ansys EM as well as HSPICE.\n\nFamiliarity with Real-Time scope, VBA, TDR.\n\nExperience with analysis of 25Gbps SERDES.\n\nExperience establishing Signal Integrity parameters to guide board routing team.\n\nCustomer facing experience with strong verbal and written communication skills.\n\nWorking knowledge of ADS, QSI/QDC, or Hyperlynx is a plus.\n\nExperience setting up, running, and summarizing Power Integrity simulations is a plus.\n\nExperience interfacing with characterization team to ensure design calculations can be collaborated with implemented board and package results is a plus.\n\n#J-18808-Ljbffr","company":"Mdaedge","rawCompany":"mdaedge","city":"Santa Clara","state":"CA","isRemote":false,"isActive":false,"createdAt":"2026-07-16T03:29:37.820Z","occupations":[{"code":"17-2061.00","title":"Computer Hardware Engineers","slug":"computer-hardware-engineers"},{"code":"17-2072.00","title":"Electronics Engineers, Except Computer","slug":"electronics-engineers-except-computer"},{"code":"17-2071.00","title":"Electrical Engineers","slug":"electrical-engineers"}],"industries":[{"code":"334111","title":"Electronic Computer Manufacturing","slug":"electronic-computer-manufacturing"},{"code":"334418","title":"Printed Circuit Assembly (Electronic Assembly) Manufacturing","slug":"printed-circuit-assembly-electronic-assembly-manufacturing"},{"code":"334413","title":"Semiconductor and Related Device Manufacturing","slug":"semiconductor-and-related-device-manufacturing"}],"jobPosting":{"@context":"https://schema.org","@type":"JobPosting","title":"Principle Hardware Design Engineer - Systems Engineering","description":"Job Summary\n\nAs a Hardware Design Principal Engineer, you'll be a member of the Central Engineering business group. If you picture it as a wheel, Central Engineering is the center hub providing IP to be used by all the other spokes on that wheel, including Automotive, Storage, Security, and Networking. You'll be part of the printed circuit board (PCB) engineering team designing boards for many different groups. Additionally, you will be designing more complex chips and boards than our competitors, for higher speeds than anyone else. We're on the leading edge of this technology and you'll love being a part of this.\n\nThe Signal Integrity Engineering candidate within the Marlborough Design Center will have opportunity to contribute to design, implementation, and check out of critical SOC validation boards. This includes setting SI specifications, SI implementation guidelines for internal and external design teams, and simulation of the design to ensure high quality results. Additional opportunities include collaboration with the package design and signal integrity teams to ensure package and board parameters are well understood. This role is for an individual contributor who will join a diverse hardware and software group that owns development and execution of package and validation board design and implementation.\n\nRequired Skills, Experience, and Knowledge\n\nHigh speed diff pair design.\n\nPCIE Gen4 or PCIE Gen5 (PAM-4 okay too).\n\nExperience with reference board design for chip validation.\n\nKnowledge of PCB design issues associated with high-speed diff pair.\n\nPower controller design – low voltage, high current, multi-phase SMPS.\n\nExperience with Power Integrity analysis.\n\nKnowledge of SI tools – Sigrity, SI Soft, HFSS.\n\nComponent Selection.\n\nSchematic capture and PCB Layout tools (Prefer Cadence Concept).\n\nCloud compute systems.\n\nPCIe Protocols.\n\nClock generation and distribution.\n\nFamiliar with Mechanical design concepts.\n\nRole & Responsibilities\n\nDesign Reference board for PCIe Gen5/6 chip.\n\nSelect and implement power scheme.\n\nCapture Schematic.\n\nWork with PCB Layout house.\n\nCreate enterprise server reference systems, using PCIe Gen5 CEM sockets, and EDSFF.\n\nWork with customers to assist with their designs, and/or implement their designs.\n\nWork with RTL team to understand and implement various features and interfaces.\n\nProvide for programming of various memories.\n\nParticipate in bring and debug of chips.\n\nMake decisions about reference designs, including connectors, cables.\n\nWork with external vendors for problems, and completing their designs.\n\nWork with SI engineers.\n\nWork with chip package vendor for package design input.\n\nKey Requirements\n\nBachelor's degree in Computer Science, Electrical Engineering or related fields and 5-10 years of related professional experience. Master's degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3-5 years of experience.\n\nExperience as Lead Signal Integrity Engineer.\n\nStrong understanding of EM fundamentals. Modeling and analysis of transmission lines, via structures, high-speed connectors, and complex BGA packages.\n\nProficiency in 2D/3D EM tools such as Sigrity Suite or Ansys EM as well as HSPICE.\n\nFamiliarity with Real-Time scope, VBA, TDR.\n\nExperience with analysis of 25Gbps SERDES.\n\nExperience establishing Signal Integrity parameters to guide board routing team.\n\nCustomer facing experience with strong verbal and written communication skills.\n\nWorking knowledge of ADS, QSI/QDC, or Hyperlynx is a plus.\n\nExperience setting up, running, and summarizing Power Integrity simulations is a plus.\n\nExperience interfacing with characterization team to ensure design calculations can be collaborated with implemented board and package results is a plus.\n\n#J-18808-Ljbffr","datePosted":"2026-07-16T03:29:37.820Z","dateModified":"2026-07-16T03:29:37.820Z","hiringOrganization":{"@type":"Organization","name":"Mdaedge","sameAs":"https://jobsearcher.com"},"jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Santa Clara","addressRegion":"CA","addressCountry":"US"}},"identifier":{"@type":"PropertyValue","name":"JobSearcher","value":"269cd0a2cb0982ced9bb17de"},"url":"https://jobsearcher.com/jobs/269cd0a2cb0982ced9bb17de"}}